公开(公告)号：US20140377909A1

公开(公告)日：2014-12-25

申请号：US14264120

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Keum-Hee MA ,  In-Young LEE ,  Moon Gi CHO ,  Chajea JO ,  Taeje CHO

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/92 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L21/568 ,  H01L21/78 ,  H01L2224/1191 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.

Abstract translation: 提供了具有通过电极的半导体封装及其制造方法。 该方法可以包括提供包括第一电路层的第一衬底，在第一衬底的前表面上形成前模层，研磨第一衬底的后表面，形成穿透第一衬底的第一贯穿电极以电 连接到第一电路层，在第一衬底的背表面上提供第二衬底，第二衬底包括电连接到第一贯通电极的第二电路层，在第一衬底的后表面上形成后模层 衬底，封装第二衬底的后模层，以及去除前模层。

公开(公告)号：US20150228591A1

公开(公告)日：2015-08-13

申请号：US14559446

申请日：2014-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang KIM ,  Keum-Hee MA ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81801 ,  H01L2224/81986 ,  H01L2224/9202 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor package including a chip stack structure having first and second chips that are secured to a dissipating plate by using a mold layer such that the second chip is combined to the dissipating plate and the first chip is bonded to the second chip, and the first chip has a smaller thickness than the second chip, a circuit board onto which the chip stack structure is mounted in a bonded manner, and an under-fill layer filling a gap space between the circuit board and first chip, a side surface of the under-fill layer being connected to a sidewall of the mold layer may be provided. Due to this bulk mounting structure, the warpage and bonding failures of the semiconductor package may be substantially reduced.

Abstract translation: 一种半导体封装，包括具有第一和第二芯片的芯片堆叠结构，所述芯片堆叠结构通过使用模具层固定到散热板，使得所述第二芯片组合到所述散热板并且所述第一芯片被结合到所述第二芯片，并且所述第一芯片 芯片具有比第二芯片小的厚度，以键合方式安装芯片堆叠结构的电路板，以及填充电路板和第一芯片之间的间隙空间的欠填充层，底部的侧表面 可以提供连接到模具层的侧壁的填充层。 由于该散装安装结构，可以显着地减少半导体封装的翘曲和接合故障。

公开(公告)号：US20140252605A1

公开(公告)日：2014-09-11

申请号：US14198713

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum-Hee MA ,  Cha-Jea JO ,  Sang-Uk HAN

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L23/3135 ,  H01L25/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568

Abstract: Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate.

Abstract translation: 提供半导体封装及其制造方法。 制造半导体封装的方法包括将多个第二半导体芯片和多个第一半导体芯片中的每一个布置在包括多个第一半导体芯片的第一晶片上彼此电连接，第一宽度 所述第一半导体芯片中的每一个大于所述第二半导体芯片的第二宽度，形成围绕所述第一晶片上的所述第二半导体芯片的第一模制层，通过锯切所述第一半导体芯片形成包括所述第一和第二半导体芯片的芯片封装 以第一半导体芯片为单位的第一晶片，将芯片封装布置在封装衬底上，以将第二半导体芯片电连接到封装衬底，以及在封装衬底上形成围绕芯片封装的第二模制层。