公开(公告)号：US20140239478A1

公开(公告)日：2014-08-28

申请号：US13803457

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Seok HONG ,  Sang-Uk HAN ,  Eun-Kyoung CHOI ,  Jong-Youn KIM ,  Hae-Jung YU ,  Cha-Jea JO

IPC: H01L23/538

CPC classification number: H01L21/561 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.

Abstract translation: 半导体器件包括至少部分地与第二半导体芯片重叠的第一半导体芯片。 第一半导体芯片耦合到衬底并且具有第一宽度，并且第二半导体芯片具有第二宽度。 该装置还包括耦合到第二半导体芯片的散热器，并具有不同于第一宽度或第二宽度中的至少一个的第三宽度。 封装模制部分至少部分地与散热器的第一区域重叠，并且不与包括散热器的顶表面的散热器的第二区域重叠。

公开(公告)号：US20160266341A1

公开(公告)日：2016-09-15

申请号：US14988739

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Cheon PARK ,  Cha-Jea JO ,  Tae-je CHO

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/42 ,  G02B6/44

CPC classification number: G02B6/43 ,  G02B6/1226 ,  G02B6/428 ,  G02B6/4283 ,  G02B6/4295 ,  G02B6/4416 ,  Y02E10/52

Abstract: A photonic integrated circuit is provided. The photonic integrated circuit includes a substrate having a through hole interconnecting a first surface and a second surface; a transmission wire passing through the through hole and including an optical transmission structure and an electrical transmission structure; and an optical-to-electrical converter connected to the optical transmission structure of the transmission wire on the first surface.

Abstract translation: 提供了一种光子集成电路。 光子集成电路包括具有互连第一表面和第二表面的通孔的基板; 传输线穿过通孔并包括光传输结构和电传输结构; 以及连接到第一表面上的传输线的光传输结构的光电转换器。

公开(公告)号：US20190174087A1

公开(公告)日：2019-06-06

申请号：US16129010

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang KIM ,  Hyo-Eun KIM ,  Jong-Bo SHIM ,  Cha-Jea JO ,  Sang-Uk HAN

IPC: H04N5/369 ,  H04N5/225 ,  G02B5/20 ,  H01L27/146

Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

公开(公告)号：US20140252605A1

公开(公告)日：2014-09-11

申请号：US14198713

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum-Hee MA ,  Cha-Jea JO ,  Sang-Uk HAN

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L23/3135 ,  H01L25/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568

Abstract: Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate.

Abstract translation: 提供半导体封装及其制造方法。 制造半导体封装的方法包括将多个第二半导体芯片和多个第一半导体芯片中的每一个布置在包括多个第一半导体芯片的第一晶片上彼此电连接，第一宽度 所述第一半导体芯片中的每一个大于所述第二半导体芯片的第二宽度，形成围绕所述第一晶片上的所述第二半导体芯片的第一模制层，通过锯切所述第一半导体芯片形成包括所述第一和第二半导体芯片的芯片封装 以第一半导体芯片为单位的第一晶片，将芯片封装布置在封装衬底上，以将第二半导体芯片电连接到封装衬底，以及在封装衬底上形成围绕芯片封装的第二模制层。

公开(公告)号：US20130299969A1

公开(公告)日：2013-11-14

申请号：US13835969

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won KIM ,  Kwang-Chul CHOI ,  Hyun-Jung SONG ,  Cha-Jea JO ,  Eun-Kyoung CHOI ,  Ji-Seok HONG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.

Abstract translation: 半导体封装包括第一半导体芯片，第二半导体芯片和密封构件。 第一半导体芯片包括具有与第一表面相对的第一表面和第二表面的基板，并且具有从第二表面以预定深度延伸的开口，以及从厚度方向从第一表面延伸的多个贯穿电极 通孔的端部通过开口的底表面露出。 第二半导体芯片被容纳在开口中并安装在开口的底表面上。 密封构件覆盖开口中的第二半导体芯片。

公开(公告)号：US20170047310A1

公开(公告)日：2017-02-16

申请号：US15183778

申请日：2016-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Bo SHIM ,  Seung-Duk BAEK ,  Cha-Jea JO ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate, a semiconductor chip and a molding member. A protrusion may be formed on a side surface of the package substrate. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the package substrate. The molding member may be formed on the upper surface and the side surface of the package substrate, and an upper surface of the protrusion. Thus, the molding member on the protrusion of the package substrate may be configured to cover the side surface of the package substrate so that the side surface of the package substrate may not be exposed.

Abstract translation: 半导体封装可以包括封装衬底，半导体芯片和模制构件。 突起可以形成在封装基板的侧表面上。 半导体芯片可以布置在封装衬底的上表面上。 半导体芯片可以与封装衬底电连接。 成型构件可以形成在封装基板的上表面和侧表面以及突起的上表面上。 因此，封装基板的突起部上的成型部件可以构成为覆盖封装基板的侧面，使得封装基板的侧面不会露出。

公开(公告)号：US20140213017A1

公开(公告)日：2014-07-31

申请号：US13803662

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Youn KIM ,  Ji-Hwang KIM ,  Hae-Jung YU ,  Cha-Jea JO

IPC: H01L21/82

CPC classification number: H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10523 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/32225 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.

Abstract translation: 制造半导体器件的方法包括：使用载体固定层将半导体衬底附着到载体上，其中半导体衬底包括多个半导体芯片。 该方法还包括在相邻芯片之间形成间隙。 可以使用一种或多种化学品或光来形成间隙，所述化学物质或光用于去除半导体衬底的部分以暴露载体固定层。 然后移除载体固定层的附加部分以允许将芯片从载体上移除。