公开(公告)号：US10580891B2

公开(公告)日：2020-03-03

申请号：US16193521

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Kim ,  Gi-Gwan Park ,  Sang-Koo Kang ,  Koung-Min Ryu ,  Jae-Hoon Lee ,  Tae-Won Ha

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US10818657B2

公开(公告)日：2020-10-27

申请号：US15233123

申请日：2016-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ki Min ,  Koung-Min Ryu ,  Sang-Koo Kang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234

Abstract: There is provided a semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer using a hybrid interlayer insulating film. The semiconductor device includes a gate electrode on a substrate, a gate spacer being on a sidewall of the gate electrode and including an upper portion and a lower portion, a lower interlayer insulating film being on the substrate and overlapping with the lower portion of the gate spacer, and an upper interlayer insulating film being on the lower interlayer insulating film and overlapping with the upper portion of the gate spacer, wherein the lower interlayer insulating film is not interposed between the upper interlayer insulating film and the upper portion of the gate spacer.

公开(公告)号：US10186615B2

公开(公告)日：2019-01-22

申请号：US15889803

申请日：2018-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Kim ,  Gi-Gwan Park ,  Song-E Kim ,  Koung-Min Ryu ,  Sun-Ki Min

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.

公开(公告)号：US09478551B2

公开(公告)日：2016-10-25

申请号：US14081543

申请日：2013-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Ju-Youn Kim ,  Koung-Min Ryu ,  Jong-Mil Youn ,  Jong-Ho Lee

IPC: H01L21/70 ,  H01L29/76 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract translation: 半导体器件包括在有源区上的沟道层，与有源区相邻的第一和第二场区以及沟道层上的栅极结构以及第一和第二场区的部分。 第一和第二场区域包括与沟道层的相应侧壁相邻的沟槽，并且沟槽的底表面在沟道层的底表面下方。

公开(公告)号：US20160020324A1

公开(公告)日：2016-01-21

申请号：US14573429

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Kwi Park ,  Koung-Min Ryu ,  Moon-Han Park ,  Hyung-suk Jung ,  Jong-hoon Baek ,  Su-Young Choi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.

Abstract translation: 半导体器件包括应力源和绝缘图案。 形成器件隔离层以限定衬底上的有源区。 在有源区上形成第一栅电极。 在器件隔离层上形成第二栅电极。 在第一栅极电极和第二栅极电极之间的有源区域中形成沟槽。 在沟槽中形成应力源。 设置在应力器和器件隔离层之间并与第二栅电极相邻的空腔。 在空腔中形成绝缘图案。

公开(公告)号：US10177253B2

公开(公告)日：2019-01-08

申请号：US15290240

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Kim ,  Gi-Gwan Park ,  Sang-Koo Kang ,  Koung-Min Ryu ,  Jae-Hoon Lee ,  Tae-Won Ha

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US10109738B2

公开(公告)日：2018-10-23

申请号：US15812527

申请日：2017-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-soo Kim ,  Song-E Kim ,  Koung-Min Ryu ,  Sun-Ki Min

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/78 ,  H01L27/12

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

公开(公告)号：US09847421B2

公开(公告)日：2017-12-19

申请号：US15189960

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-soo Kim ,  Song-E Kim ,  Koung-Min Ryu ,  Sun-Ki Min

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L27/1233 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7854

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

公开(公告)号：US09793399B2

公开(公告)日：2017-10-17

申请号：US14573429

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Kwi Park ,  Koung-Min Ryu ,  Moon-Han Park ,  Hyung-suk Jung ,  Jong-hoon Baek ,  Su-Young Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.