公开(公告)号：US20240128347A1

公开(公告)日：2024-04-18

申请号：US18397700

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28132 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20240222453A1

公开(公告)日：2024-07-04

申请号：US18228376

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Bok LEE ,  Rak Hwan KIM ,  Jong Min BAEK ,  Moon Kyun SONG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/775

Abstract: A semiconductor device includes an interlayer insulating film including a first surface and a second surface opposite to the first surface in a first direction; a source/drain pattern provided in the interlayer insulating film; a channel pattern adjacent to the source/drain pattern in a second direction and contacting the source/drain pattern; a front wiring provided on the first surface of the interlayer insulating film; a back wiring provided on the second surface of the interlayer insulating film; and a first connecting via contact and a second connecting via contact which are provided between the source/drain pattern and the back wiring and connected to the source/drain pattern.

公开(公告)号：US20180166334A1

公开(公告)日：2018-06-14

申请号：US15668029

申请日：2017-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Rak Hwan KIM ,  Byung Hee KIM ,  Sang Bom KANG ,  Jong Jin LEE ,  Eun Ji JUNG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.

公开(公告)号：US20210210613A1

公开(公告)日：2021-07-08

申请号：US17015296

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20250072096A1

公开(公告)日：2025-02-27

申请号：US18606375

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Woong SHIM ,  Seong Heum CHOI ,  Do Sun LEE ,  Hyo Seok CHOI ,  Rak Hwan KIM ,  Chung Hwan SHIN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

公开(公告)号：US20240405090A1

公开(公告)日：2024-12-05

申请号：US18390782

申请日：2023-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Heum CHOI ,  Jeong Hoon SEO ,  Rak Hwan KIM ,  Chung Hwan SHIN ,  Do Sun LEE

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/40

Abstract: A semiconductor device is provided. The semiconductor device includes: a semiconductor device including: an active pattern extending in a first direction; a gate structure including a gate electrode extending in a second direction and a gate spacer on the active pattern, wherein the gate electrode and the gate spacer are spaced apart from each other in the first direction; a source/drain pattern on the active pattern; a contact barrier layer on the source/drain pattern; and a contact filling layer on the contact barrier layer. An uppermost point of the contact barrier layer is between an upper surface of the contact filling layer and a lower surface of the contact filling layer, and outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane.

公开(公告)号：US20240332381A1

公开(公告)日：2024-10-03

申请号：US18382395

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Won KANG ,  Chung Hwan SHIN ,  Seong Heum CHOI ,  Rak Hwan KIM

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device may include an active pattern extending in a first direction, a gate structure which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction, a gate contact on the gate structure, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a via plug on the source/drain contact. An upper surface of the gate contact and a second upper surface of the via plug may be placed on the same plane. A lower surface of the gate contact and a lower surface of the via plug may be different in height, on the basis of an upper surface of the active pattern.

公开(公告)号：US20220319916A1

公开(公告)日：2022-10-06

申请号：US17838740

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Keun CHUNG ,  Joon Gon LEE ,  Rak Hwan KIM ,  Chung Hwan SHIN ,  Do Sun LEE ,  Nam Gyu CHO

IPC: H01L21/768

Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.

公开(公告)号：US20240120274A1

公开(公告)日：2024-04-11

申请号：US18217012

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Rak Hwan KIM ,  Jong Min BAEK ,  Moon Kyun SONG

IPC: H01L23/522 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/088

Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.

公开(公告)号：US20220285518A1

公开(公告)日：2022-09-08

申请号：US17826380

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/786

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.