公开(公告)号：US20200279176A1

公开(公告)日：2020-09-03

申请号：US16448842

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. HATCHER ,  Titash RAKSHIT ,  Jorge KITTL ,  Rwik SENGUPTA ,  Dharmendar PALLE ,  Joon Goo HONG

IPC: G06N5/04 ,  G11C11/16 ,  G11C13/00 ,  G11C11/22 ,  G06F17/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

公开(公告)号：US20150364542A1

公开(公告)日：2015-12-17

申请号：US14737048

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. RODDER ,  Borna OBRADOVIC ,  Rwik SENGUPTA ,  Dharmendar Reddy PALLE ,  Robert C. BOWEN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/20

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/755

Abstract: An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.

Abstract translation: 集成电路可以包括多个第一，非Si，纳米片状场效应晶体管（FET）和多个第二，Si，纳米片FET。 第一非硅纳米片FET的纳米片可以包括少于约30％的Si。 第一个非Si纳米片FET可以限定集成电路的电路的临界速度路径。 第二，Si，纳米片FET的纳米片可以包括大于约30％的Si。 第二个Si纳米片FET可以定义集成电路的非临界速度路径。 第一非硅纳米片FET的结构可以被配置为具有比第二Si纳米片FET的速度更高的速度。

公开(公告)号：US20150318355A1

公开(公告)日：2015-11-05

申请号：US14698817

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E WANG ,  Mark S. RODDER ,  Rwik SENGUPTA

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795

Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

Abstract translation: 通过在体硅（Si）衬底的表面上直接形成第一硅 - 锗（SiGe）层来形成应变消除缓冲器。 图案化第一SiGe层以形成至少两个SiGe结构，因此在SiGe结构之间存在空间。 在SiGe结构上形成氧化物，SiGe结构被台面退火。 去除氧化物以暴露SiGe结构的顶部。 在SiGe结构的暴露部分上形成第二SiGe层，使得第二SiGe层覆盖SiGe结构之间的空间，并且使得第一和第二SiGe层的Ge含量百分比基本相等。 SiGe结构之间的空间与与空间相邻的结构的尺寸以及与结构相关联的应力释放量有关。

公开(公告)号：US20200295134A1

公开(公告)日：2020-09-17

申请号：US16711582

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho DO ,  Rwik SENGUPTA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

公开(公告)号：US20160133513A1

公开(公告)日：2016-05-12

申请号：US14920867

申请日：2015-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh HEGDE ,  Mark RODDER ,  Rwik SENGUPTA ,  Chris BOWEN

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier.

Abstract translation: 公开了一种用于形成金属 - 氧硅酸盐扩散屏障用于大马士革金属化的方法。 在层间电介质（ILD）材料中形成沟槽。 在沟槽中形成包含硅，碳，氧，ILD的组成成分或其组合的氧硅酸盐形成增强层。 在氧硅酸盐形成增强层上形成阻挡种子层，其包含选自第一组元素金属的元素金属和选自第二组元素金属的元素金属。 第二组中的元素金属在铜或其合金中是不混溶的，其扩散常数大于铜或其合金的自扩散; 在氧硅酸盐形成过程中不会降低硅 - 氧键; 并且促进铜或铜合金与金属 - 氧硅酸盐屏障扩散层的粘附。 然后将该结构退火以形成金属 - 氧硅酸盐扩散阻挡层。

公开(公告)号：US20150084097A1

公开(公告)日：2015-03-26

申请号：US14312702

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyeon JEON ,  Rwik SENGUPTA ,  Chulhong PARK ,  Kwanyoung CHUN ,  Yusun LEE ,  Hyun-Jong LEE

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线，并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。