Abstract:
A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.
Abstract:
An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.
Abstract:
An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.
Abstract:
A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.
Abstract:
Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.
Abstract:
A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.
Abstract:
A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.
Abstract:
A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.