公开(公告)号：US20170338328A1

公开(公告)日：2017-11-23

申请号：US15276784

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E WANG ,  Mark S. RODDER ,  Borna J. OBRADOVIC ,  Dharmendar Reddy PALLE ,  Joon Goo HONG

IPC: H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US20150364556A1

公开(公告)日：2015-12-17

申请号：US14728104

申请日：2015-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. RODDER ,  Dharmendar Reddy PALLE ,  Borna J. Obradovic

IPC: H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886

Abstract: An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.

Abstract translation: 集成电路芯片包括半导体衬底，第一后端线单元电路，其包括第一组场效应晶体管，第二栅极负载单元电路，其包括第二组场效应晶体管。 第一组场效应晶体管包括第一晶体管，第二组场效应晶体管包括第二晶体管。 与第二晶体管的栅电极的底表面相比，第一晶体管的栅电极的底表面比半导体衬底的底表面更靠近。

公开(公告)号：US20150364542A1

公开(公告)日：2015-12-17

申请号：US14737048

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. RODDER ,  Borna OBRADOVIC ,  Rwik SENGUPTA ,  Dharmendar Reddy PALLE ,  Robert C. BOWEN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/20

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/755

Abstract: An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.

Abstract translation: 集成电路可以包括多个第一，非Si，纳米片状场效应晶体管（FET）和多个第二，Si，纳米片FET。 第一非硅纳米片FET的纳米片可以包括少于约30％的Si。 第一个非Si纳米片FET可以限定集成电路的电路的临界速度路径。 第二，Si，纳米片FET的纳米片可以包括大于约30％的Si。 第二个Si纳米片FET可以定义集成电路的非临界速度路径。 第一非硅纳米片FET的结构可以被配置为具有比第二Si纳米片FET的速度更高的速度。

公开(公告)号：US20150318355A1

公开(公告)日：2015-11-05

申请号：US14698817

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E WANG ,  Mark S. RODDER ,  Rwik SENGUPTA

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795

Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

Abstract translation: 通过在体硅（Si）衬底的表面上直接形成第一硅 - 锗（SiGe）层来形成应变消除缓冲器。 图案化第一SiGe层以形成至少两个SiGe结构，因此在SiGe结构之间存在空间。 在SiGe结构上形成氧化物，SiGe结构被台面退火。 去除氧化物以暴露SiGe结构的顶部。 在SiGe结构的暴露部分上形成第二SiGe层，使得第二SiGe层覆盖SiGe结构之间的空间，并且使得第一和第二SiGe层的Ge含量百分比基本相等。 SiGe结构之间的空间与与空间相邻的结构的尺寸以及与结构相关联的应力释放量有关。

公开(公告)号：US20170263748A1

公开(公告)日：2017-09-14

申请号：US15276779

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Joon Goo HONG ,  Dharmendar Reddy PALLE ,  Mark S. RODDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

公开(公告)号：US20170263728A1

公开(公告)日：2017-09-14

申请号：US15267134

申请日：2016-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Ganesh HEGDE ,  Robert Christopher BOWEN ,  Borna J. OBRADOVIC ,  Mark S. RODDER

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02485 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/7853

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.

公开(公告)号：US20170263704A1

公开(公告)日：2017-09-14

申请号：US15289951

申请日：2016-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Joon Goo HONG ,  Dharmendar Reddy PALLE ,  Mark S. RODDER

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/786

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

公开(公告)号：US20160035675A1

公开(公告)日：2016-02-04

申请号：US14809266

申请日：2015-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh HEGDE ,  Mark S. RODDER ,  Jorge A. KITTL ,  Robert C. BOWEN

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

Abstract translation: 可以通过在ILD中形成沟槽来形成镶嵌互连结构。 扩散阻挡层可以沉积在沟槽表面上，随后是第一衬里材料。 可以从沟槽的底表面去除第一衬里材料。 第二衬里材料可以定向沉积在底部。 可以在第一和第二衬垫材料上沉积导电种子层，并且导电材料可以填充在沟槽中。 CMP工艺可以从结构的顶部去除多余的材料。 镶嵌互连件可以包括具有沟槽的电介质，布置在沟槽侧壁上的第一衬垫层和布置在沟槽底部上的第二衬垫层。 导电材料可以填充沟槽。 第一衬里材料可以具有低润湿性，并且第二衬里材料相对于导电材料可具有高润湿性。