INTEGRATED CIRCUIT CHIPS HAVING FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE DESIGNS
    2.
    发明申请
    INTEGRATED CIRCUIT CHIPS HAVING FIELD EFFECT TRANSISTORS WITH DIFFERENT GATE DESIGNS 有权
    具有不同栅极设计的场效应晶体管的集成电路芯片

    公开(公告)号:US20150364556A1

    公开(公告)日:2015-12-17

    申请号:US14728104

    申请日:2015-06-02

    Abstract: An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.

    Abstract translation: 集成电路芯片包括半导体衬底,第一后端线单元电路,其包括第一组场效应晶体管,第二栅极负载单元电路,其包括第二组场效应晶体管。 第一组场效应晶体管包括第一晶体管,第二组场效应晶体管包括第二晶体管。 与第二晶体管的栅电极的底表面相比,第一晶体管的栅电极的底表面比半导体衬底的底表面更靠近。

    METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS
    4.
    发明申请
    METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS 有权
    在绝缘体上形成无缺陷SRB的方法和绝缘子上的无缺陷FIS

    公开(公告)号:US20150318355A1

    公开(公告)日:2015-11-05

    申请号:US14698817

    申请日:2015-04-28

    Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

    Abstract translation: 通过在体硅(Si)衬底的表面上直接形成第一硅 - 锗(SiGe)层来形成应变消除缓冲器。 图案化第一SiGe层以形成至少两个SiGe结构,因此在SiGe结构之间存在空间。 在SiGe结构上形成氧化物,SiGe结构被台面退火。 去除氧化物以暴露SiGe结构的顶部。 在SiGe结构的暴露部分上形成第二SiGe层,使得第二SiGe层覆盖SiGe结构之间的空间,并且使得第一和第二SiGe层的Ge含量百分比基本相等。 SiGe结构之间的空间与与空间相邻的结构的尺寸以及与结构相关联的应力释放量有关。

    LOW RESISTIVITY DAMASCENE INTERCONNECT
    8.
    发明申请
    LOW RESISTIVITY DAMASCENE INTERCONNECT 有权
    低电阻大气互连

    公开(公告)号:US20160035675A1

    公开(公告)日:2016-02-04

    申请号:US14809266

    申请日:2015-07-26

    Abstract: A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

    Abstract translation: 可以通过在ILD中形成沟槽来形成镶嵌互连结构。 扩散阻挡层可以沉积在沟槽表面上,随后是第一衬里材料。 可以从沟槽的底表面去除第一衬里材料。 第二衬里材料可以定向沉积在底部。 可以在第一和第二衬垫材料上沉积导电种子层,并且导电材料可以填充在沟槽中。 CMP工艺可以从结构的顶部去除多余的材料。 镶嵌互连件可以包括具有沟槽的电介质,布置在沟槽侧壁上的第一衬垫层和布置在沟槽底部上的第二衬垫层。 导电材料可以填充沟槽。 第一衬里材料可以具有低润湿性,并且第二衬里材料相对于导电材料可具有高润湿性。

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