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公开(公告)号：US11495541B2
公开(公告)日：2022-11-08
申请号：US16592886
申请日：2019-10-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon Lim , Sang-Wan Nam , Sang-Won Park , Sang-Won Shim , Hongsoo Jeon , Yonghyuk Choi
IPC: H01L23/535 , H01L27/11573 , H01L27/11582
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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2.发明授权公开(公告)号：US11043274B2
公开(公告)日：2021-06-22
申请号：US16851622
申请日：2020-04-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yonghyuk Choi , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
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公开(公告)号：US10388367B2
公开(公告)日：2019-08-20
申请号：US15351552
申请日：2016-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Dongkyo Shim , Kitae Park , Sang-Won Shim
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
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公开(公告)号：US11515325B2
公开(公告)日：2022-11-29
申请号：US17025479
申请日：2020-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon Lim , Sang-Wan Nam , Sang-Won Park , Sang-Won Shim , Hongsoo Jeon , Yonghyuk Choi
IPC: H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L23/522 , G11C7/18 , H01L27/11556 , H01L27/11526 , G11C8/14 , H01L27/11519
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
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公开(公告)号：US10699782B2
公开(公告)日：2020-06-30
申请号：US16503169
申请日：2019-07-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Dongkyo Shim , Kitae Park , Sang-Won Shim
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
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Patent Agency Ranking
6.发明授权Nonvolatile memory device and method controlling word line setup time based on difference in setup voltage levels 有权非易失性存储器件和方法基于设置电压电平差异来控制字线建立时间公开(公告)号：US09502124B2
公开(公告)日：2016-11-22
申请号：US14322335
申请日：2014-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Dongkyo Shim , Kitae Park , Sang-Won Shim
CPC classification number: G11C11/5642 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C29/021 , G11C29/028
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
Abstract translation: 非易失性存储器件包括：电压发生器，其向存储单元阵列的字线依次提供第一设定电压和第二设定电压;以及控制逻辑，包括时间控制单元，所述时间控制单元确定所述字线的字线建立时间 基于所述第一和第二设定电压之间的差，将所述第二设置电压提供给所述第二设置电压。
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公开(公告)号：US11198154B2
公开(公告)日：2021-12-14
申请号：US16488507
申请日：2018-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Won Shim , Yonggu Lee , Joongsam Yun , Minkoo Kang
Abstract: Disclosed are a method and an apparatus for converting a musical element so as to provide a vibration in an electronic device. According to various embodiments of the present invention, an electronic device may comprise: a display; a vibration generation apparatus for generating a vibration; and a processor functionally connected to the display and the vibration generation apparatus, wherein the processor is configured to: select multiple frequencies, using a musical element; set at least one vibration on the basis of the selected multiple frequencies; and generate a vibration pattern on the basis of the set vibration. Various elements are possible.
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8.发明申请公开(公告)号：US20210065805A1
公开(公告)日：2021-03-04
申请号：US16851622
申请日：2020-04-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Jae-Duk Yu , Kang-Bin Lee , Sang-Won Shim , Bongsoon Lim
Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.
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公开(公告)号：US10410728B2
公开(公告)日：2019-09-10
申请号：US15908051
申请日：2018-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Shim
Abstract: A nonvolatile memory device for reducing hot-carrier injection (HCI) and a programming method of the nonvolatile memory device, the programming method of the nonvolatile memory device includes programming memory cells included in a cell string in a direction from an upper memory cell adjacent to a string selection transistor to a lower memory cell adjacent to a ground selection transistor from among a plurality of memory cells; when a selected memory cell is programmed, applying a first inhibition voltage to first non-selected word lines connected to first non-selected memory cells located over the selected memory cell; and applying a second inhibition voltage to second non-selected word lines connected to second non-selected memory cells located under the selected memory cell when a predetermined delay time elapses after the first inhibition voltage is applied.
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10.发明授权公开(公告)号：US09870833B2
公开(公告)日：2018-01-16
申请号：US15425557
申请日：2017-02-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bongsoon Lim , Seokmin Yoon , Sang-Won Shim
CPC classification number: G11C16/3459 , G06F11/2094 , G11C7/106 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device may include a cell array, a first page buffer, and a second page buffer. The first page buffer may be connected to a first memory cell of the cell array and may store first sensing data generated by sensing whether a program operation of the first memory cell is completed during a program verify operation. The second page buffer may be connected to a second memory cell of the cell array. During the program verify operation, the second page buffer may generate and store first verify data based on second sensing data generated by sensing whether a program operation of the second memory cell is completed, may receive the first sensing data from the first page buffer, and may store second verify data generated by accumulating the first sensing data and the first verify data.
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