公开(公告)号：US11984426B2

公开(公告)日：2024-05-14

申请号：US17890835

申请日：2022-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun Ahn

IPC: H01L23/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L25/18 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package is provided. The semiconductor package includes: a package substrate having a first surface, a second surface that is provided opposite the first surface and has a concave portion, and a through-hole having a side surface that is oblique with respect to the first surface, and a first diameter of a first opening of the through-hole defined through the first surface being less than a second diameter of a second opening of the through-hole defined through a bottom surface of the concave portion; a plurality of first semiconductor chips provided on the first surface; a second semiconductor chip provided on the bottom surface; and a molding portion provided in the through-hole, and covering the plurality of first semiconductor chips and the second semiconductor chip.

公开(公告)号：US11424218B2

公开(公告)日：2022-08-23

申请号：US16844642

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun Ahn

IPC: H01L23/13 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package is provided. The semiconductor package includes: a package substrate having a first surface, a second surface that is provided opposite the first surface and has a concave portion, and a through-hole having a side surface that is oblique with respect to the first surface, and a first diameter of a first opening of the through-hole defined through the first surface being less than a second diameter of a second opening of the through-hole defined through a bottom surface of the concave portion; a plurality of first semiconductor chips provided on the first surface; a second semiconductor chip provided on the bottom surface; and a molding portion provided in the through-hole, and covering the plurality of first semiconductor chips and the second semiconductor chip.

公开(公告)号：US20240063103A1

公开(公告)日：2024-02-22

申请号：US18236090

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Seokhyun Lee ,  Seokgeun Ahn ,  Hwanyoung Choi

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L25/105 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L23/3107 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1579 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15184

Abstract: A semiconductor package includes a first redistribution structure including a top surface, a chip arranged on the top surface of the first redistribution structure the chip having a top surface, bottom surface, and side surfaces, and a package body arranged on the top surface of the first redistribution structure to cover the side surfaces of the chip. The first redistribution structure includes a plurality of redistribution layers stacked in a vertical direction, a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other, a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other, and a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers.

公开(公告)号：US20240021577A1

公开(公告)日：2024-01-18

申请号：US18121374

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Seokgeun Ahn ,  Younglyong Kim

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H10B80/00 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/5386 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/08112 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/182

Abstract: In some embodiments, a semiconductor package includes a package substrate, a plurality of semiconductor chips on the package substrate, a plurality of interposers between the package substrate and the plurality of semiconductor chips, and a molding layer in contact with the plurality of semiconductor chips and the plurality of interposers. The plurality of semiconductor chips includes a first semiconductor chip, and a second and a third semiconductor chip spaced apart from the first semiconductor chip in horizontal directions. The plurality of interposers includes a first vertical connection interposer vertically overlapping the first semiconductor chip, a second vertical connection interposer vertically overlapping the second semiconductor chip, a first horizontal connection interposer vertically overlapping the first and the second semiconductor chips, and a second horizontal connection interposer vertically overlapping the second and the third semiconductor chips.

公开(公告)号：US20240421140A1

公开(公告)日：2024-12-19

申请号：US18628182

申请日：2024-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Lee ,  Yeongbeom Ko ,  Seokgeun Ahn ,  Juhyeon Oh ,  Gwangjae Jeon

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, and a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core. The first gap filling portion and the second gap filling portion are directly bonded to each other.

公开(公告)号：US20230317678A1

公开(公告)日：2023-10-05

申请号：US18170633

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokgeun Ahn

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651

Abstract: A semiconductor package, includes: a first semiconductor chip including first connection pads on the first front surface, and through electrodes extending perpendicularly to the first rear surface and electrically connected to at least a portion of the first connection pads; a second semiconductor chip including second connection pads on the second front surface, and on the first rear surface so that the second rear surface faces the first semiconductor chip; a dielectric layer on the second semiconductor chip; first conductive structures in the dielectric layer, and connecting the through electrodes of a first group and the second connection pads; second conductive structures in the dielectric layer, and having first and second ends, the first ends connected to the through electrodes of a second group and at least a portion of the second ends thereof being exposed from the dielectric layer; at least one third semiconductor chip including third connection pads on the third front surface, and on the dielectric layer so that the third rear surface faces the second semiconductor chip; conductive wires connecting the second conductive structures and the third connection pads.

公开(公告)号：US20240413026A1

公开(公告)日：2024-12-12

申请号：US18658546

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom KO ,  Seokgeun Ahn ,  Juhyeon Oh ,  Sanghoon Lee ,  Gwangjae Jeon

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a buffer die, a plurality of core die blocks sequentially stacked on the buffer die, and a molding member on the buffer die and covering outer surfaces of the plurality of core die blocks. Each of the plurality of core die blocks includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and a first gap filling portion, a third semiconductor chip disposed on the second semiconductor chip and a second gap filling portion, and a fourth semiconductor chip disposed on the third semiconductor chip.

公开(公告)号：US20240170358A1

公开(公告)日：2024-05-23

申请号：US18378603

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokgeun Ahn ,  Cheol Kim ,  Hwanyoung Choi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A semiconductor package includes a lower redistribution structure, a first semiconductor chip and a second semiconductor chip that stacked on the lower redistribution structure, the second semiconductor chip including a heat dissipation pad disposed at an upper surface of the second semiconductor chip, a lower conductive pillar disposed on the lower redistribution structure, an upper conductive pillar disposed on the lower conductive pillar, a heat dissipation pillar disposed on the heat dissipation pad, an upper redistribution structure disposed on the upper conductive pillar; and a heat dissipation structure disposed on the heat dissipation pillar.

公开(公告)号：US20240014086A1

公开(公告)日：2024-01-11

申请号：US18135541

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun Ahn ,  Seokhyun Lee ,  Hwanyoung Choi

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L25/0657 ,  H01L23/49838 ,  H01L21/563 ,  H01L24/05 ,  H01L23/5226 ,  H01L24/16 ,  H01L2224/04105 ,  H01L2225/06544 ,  H01L2224/05009 ,  H01L2224/16227 ,  H01L2924/182

Abstract: A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.

公开(公告)号：US20210066245A1

公开(公告)日：2021-03-04

申请号：US16844642

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun Ahn

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/13

Abstract: A semiconductor package is provided. The semiconductor package includes: a package substrate having a first surface, a second surface that is provided opposite the first surface and has a concave portion, and a through-hole having a side surface that is oblique with respect to the first surface, and a first diameter of a first opening of the through-hole defined through the first surface being less than a second diameter of a second opening of the through-hole defined through a bottom surface of the concave portion; a plurality of first semiconductor chips provided on the first surface; a second semiconductor chip provided on the bottom surface; and a molding portion provided in the through-hole, and covering the plurality of first semiconductor chips and the second semiconductor chip.