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    Memory system architecture including semi-network topology with shared output channels
    1.
    发明授权
    Memory system architecture including semi-network topology with shared output channels 有权

    公开(公告)号：US10127165B2

    公开(公告)日：2018-11-13

    申请号：US14801241

    申请日：2015-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit Berman ,  Uri Beitler ,  Jun Jin Kong

    IPC: G06F13/28 ,  G06F3/06

    Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

    LOW-POWER DATA TRANSFER FROM BUFFER TO FLASH MEMORY
    2.
    发明申请
    LOW-POWER DATA TRANSFER FROM BUFFER TO FLASH MEMORY 审中-公开

    公开(公告)号：US20190180793A1

    公开(公告)日：2019-06-13

    申请号：US15836067

    申请日：2017-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： AMIT BERMAN ,  Junjin KONG ,  Uri Beitler

    IPC: G11C5/14 ,  G11C11/24 ,  G06F3/06 ,  G11C11/00

    Abstract: A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.

    Joint source-channel encoding and decoding for compressed and uncompressed data
    4.
    发明授权
    Joint source-channel encoding and decoding for compressed and uncompressed data 有权
    用于压缩和未压缩数据的联合源通道编码和解码

    公开(公告)号：US09391646B2

    公开(公告)日：2016-07-12

    申请号：US14224572

    申请日：2014-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Iddo Naiss ,  Uri Beitler ,  Jun Jin Kong

    IPC: G06F11/00 ,  H03M13/00 ,  H03M13/11 ,  G06F11/10

    CPC classification number: H03M13/6312 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/152

    Abstract: A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.

    Abstract translation: 存储器控制器包括联合源通道编码器电路和联合源通道解码器电路。 联合源信道编码器电路源对接收到的数据进行编码，独立于接收到的数据是否是可压缩数据，对源编码数据执行纠错编码，并将源编码数据存储在存储器件中。 联合源信道解码器电路在读取数据的纠错编码的迭代之间对从存储器件读取的数据执行源解码，并将读取的数据输出到缓冲存储器和存储设备接口中的至少一个。 联合源信道解码器电路执行读取数据的源解码，与读数据是否为压缩数据无关。

    MEMORY DEVICES AND METHODS FOR OPERATING THE SAME
    7.
    发明申请
    MEMORY DEVICES AND METHODS FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20170337967A1

    公开(公告)日：2017-11-23

    申请号：US15156956

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Jun Jin Kong ,  Uri Beitler

    IPC: G11C11/56

    CPC classification number: G11C11/5628 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5648

    Abstract: A memory device includes a memory including memory cells, each of the memory cells being configured to store multiple bits of data. The memory device includes a controller configured to map the levels of the memory cells to bits such that a first half of the levels have a bit with a first binary value in a desired bit position and a second half of the levels have a bit with a second binary value in the desired bit position. The first half of the levels are a first group of consecutive levels, and the second half of the levels are a second group of consecutive levels. The controller is configured to generate a distribution for writing the data to the memory cells based on the mapping, and write the data to the memory cells based on the determined distribution.

    LEVEL-OCCUPATION REDUCTION IN MLC WORDLINE FOR IMPROVED MEMORY IOPS
    10.
    发明申请
    LEVEL-OCCUPATION REDUCTION IN MLC WORDLINE FOR IMPROVED MEMORY IOPS 有权
    在改进的内存IOPS中，MLC WORDLINE中的级别减少

    公开(公告)号：US20160211028A1

    公开(公告)日：2016-07-21

    申请号：US14600754

    申请日：2015-01-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Amit Berman ,  Uri Beitler ,  Jun Jin Kong

    IPC: G11C16/24 ,  G11C16/32

    CPC classification number: G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2207/102

    Abstract: A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.

    Abstract translation: 提供了一种操作存储器件的方法。 存储器件包括多个多级存储器单元，每个存储器单元包括L级。 接收以二进制数表示的数据。 从数据生成P长度字符串。 P长度字符串转换为Q长度字符串。 通过从L级消除至少一个级别，使用I级分布Q长度字符串。 P和Q表示P长度字符串和Q长度字符串的二进制位长度。 Q大于P。L表示每个多级存储器单元具有的最大级别数。 I小于L.将Q长度的串编程到多个存储单元中。

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