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    ASYNCHRONOUS INTERFACE IN A SYSTEM ON CHIP AND A METHOD OF OPERATING THE SAME
    4.
    发明申请
    ASYNCHRONOUS INTERFACE IN A SYSTEM ON CHIP AND A METHOD OF OPERATING THE SAME 审中-公开
    芯片系统中的异步接口及其操作方法

    公开(公告)号：US20170052910A1

    公开(公告)日：2017-02-23

    申请号：US15344931

    申请日：2016-11-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hee-Seong LEE ,  Woo-Jin KIM ,  Nak Hee SEONG

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/36

    CPC classification number: G06F13/1689 ,  G06F1/12 ,  G06F1/324 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/42 ,  Y02D10/126 ,  Y02D10/151

    Abstract: A mobile system includes a first interface configured to transmit a payload in synchronization with a first clock signal through a first channel at a first transfer rate; and a second interface that includes: a payload storage connected to the first channel and configured to receive the payload from the first channel; and a payload receiver connected to the payload storage and configured to receive the payload from the payload storage in synchronization with a second clock at a second transfer rate through a second channel. A length of the second channel is shorter than a length of the first channel, and the first clock signal is asynchronous with the second clock signal.

    Abstract translation: 移动系统包括：第一接口，被配置为以第一传输速率通过第一信道与第一时钟信号同步发送有效载荷; 以及第二接口，其包括：连接到所述第一信道并被配置为从所述第一信道接收所述有效载荷的有效载荷存储器; 以及有效载荷接收器，其连接到所述有效载荷存储器并且被配置为以与所述第二信道的第二传送速率的第二时钟同步地从所述有效负载存储器接收所述有效载荷 第二通道的长度小于第一通道的长度，并且第一时钟信号与第二时钟信号是异步的。

    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE
    5.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开

    公开(公告)号：US20200098977A1

    公开(公告)日：2020-03-26

    申请号：US16366136

    申请日：2019-03-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woo-Jin KIM ,  Shin-Hee HAN

    IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

    Abstract: A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.

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