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    Systems, methods, and computer program products for transistor compact modeling using artificial neural networks
    1.
    发明授权
    Systems, methods, and computer program products for transistor compact modeling using artificial neural networks 有权

    公开(公告)号：US12223246B2

    公开(公告)日：2025-02-11

    申请号：US17465361

    申请日：2021-09-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jing Wang ,  Woosung Choi

    IPC: G06F30/367 ,  G06N3/08 ,  G06F119/02

    Abstract: A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; and in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network.

    Shield structure in electronic device and operation method thereof
    9.
    发明授权
    Shield structure in electronic device and operation method thereof 有权

    公开(公告)号：US12256486B2

    公开(公告)日：2025-03-18

    申请号：US18115992

    申请日：2023-03-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jonghyuk Kim ,  Sangdeok Lee ,  Woosung Choi

    IPC: H05K1/02 ,  H05K1/18 ,  H05K9/00

    Abstract: Various embodiments of the present disclosure relate to a package structure capable of allowing a shield used for noise attenuation to be used for other purposes, in an electronic device in which components are arranged at high density, and an operation method for preventing/reducing noise radiation or detecting in advance defects in a manufacturing process using the same. For this, an electronic device may include: a printed circuit board (PCB), and a package disposed on the printed circuit board. The package may include: a ground pad and at least one shield pad connected to the printed circuit board, a laminated structure comprising a plurality of laminated ground layers electrically connected to the ground pad by at least one via hole, at least one electronic component disposed on an uppermost surface of the plurality of laminated ground layers, a shield covering the at least one electronic component, wherein the at least one component is not exposed to the outside, and at least one switch device comprising a switch including a first terminal electrically connected to the shield through a first conductor wiring, a second terminal electrically connected to one of the plurality of ground layers through a second conductor wiring, and a third terminal electrically connected to the shield pad through a third conductor wiring and disposed on the uppermost surface and configured to selectively connect the first terminal to the second terminal or the third terminal wherein the shield is connected to one of the one ground layer or the shield pad.

    System and method for compact neural network modeling of transistors
    10.
    发明授权
    System and method for compact neural network modeling of transistors 有权

    公开(公告)号：US11537841B2

    公开(公告)日：2022-12-27

    申请号：US16430219

    申请日：2019-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jing Wang ,  Woosung Choi

    IPC: G06N3/04 ,  G06F119/12 ,  G06N3/08 ,  G06F30/33

    Abstract: A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

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