公开(公告)号：US12087744B2

公开(公告)日：2024-09-10

申请号：US18125170

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/3511

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US11901276B2

公开(公告)日：2024-02-13

申请号：US18153601

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho Jang ,  Jongyoun Kim ,  Jungho Park ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US11145611B2

公开(公告)日：2021-10-12

申请号：US16795795

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US12261104B2

公开(公告)日：2025-03-25

申请号：US17670635

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Dongkyu Kim ,  Minjung Kim ,  Yeonho Jang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.

公开(公告)号：US11637081B2

公开(公告)日：2023-04-25

申请号：US17474614

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US11569157B2

公开(公告)日：2023-01-31

申请号：US16946209

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho Jang ,  Jongyoun Kim ,  Jungho Park ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US11094636B2

公开(公告)日：2021-08-17

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Inwon O ,  Jongyoun Kim ,  Seokhyun Lee ,  Yeonho Jang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L23/66 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

公开(公告)号：US20240136250A1

公开(公告)日：2024-04-25

申请号：US18197998

申请日：2023-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho Jang ,  Inhyung Song ,  Kyungdon Mun ,  Hyeonjeong Hwang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/3738 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/165 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.

公开(公告)号：US20240065002A1

公开(公告)日：2024-02-22

申请号：US18231341

申请日：2023-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Joonsung Kim ,  Inhyung Song ,  Yeonho Jang

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/96 ,  H01L2224/214 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L24/32 ,  H01L2224/32145 ,  H01L24/33 ,  H01L2224/33181 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/17181 ,  H01L24/16 ,  H01L24/17 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/16145

Abstract: A semiconductor device including a first lower buffer chip, an upper buffer chip disposed on an upper surface of the first lower buffer chip, a plurality of conductive posts spaced apart from the first lower buffer chip and disposed on a lower surface of the upper buffer chip, and a first memory chip stack structure disposed on the upper buffer chip and including a plurality of first memory chips.

公开(公告)号：US11869835B2

公开(公告)日：2024-01-09

申请号：US17892215

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Jongyoun Kim ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49816

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.