公开(公告)号：US20240063167A1

公开(公告)日：2024-02-22

申请号：US18217649

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Inhyo HWANG

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/32 ,  H01L25/105 ,  H01L25/0657 ,  H01L23/3135 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/16148 ,  H01L2224/08148 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/83203 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1431

Abstract: A semiconductor package includes: a buffer die; a first core die disposed on the buffer die; a second core die disposed on the first core die; a first non-conductive film (NCF) disposed between the first core die and the second core die and bonding the first core die and the second core die to each other; a first molding layer at least partially surrounding a side surface of the first core die; and a second molding layer surrounding the first NCF and the first molding layer, wherein the first core die, the second core die, and the buffer die are disposed on the second molding layer, wherein a side surface of the first molding layer and a side surface of the first NCF form a coplanar surface.

公开(公告)号：US20230154910A1

公开(公告)日：2023-05-18

申请号：US17899025

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Sangcheon PARK

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05666 ,  H01L2224/05686 ,  H01L2224/80379 ,  H01L2224/13147 ,  H01L24/13

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having a front surface and a rear surface, a first insulating layer on the rear surface, a recess portion extending into the first substrate through the first insulating layer, a protective insulating layer extending along an inner side surface and a bottom surface of the recess portion, a through electrode extending from the front surface through the bottom surface of the recess portion and the protective insulating layer, and a first connection pad contacting the through electrode in the recess portion, and surrounded by the protective insulating layer, the first semiconductor chip having a flat upper surface defined by upper surfaces of the first insulating layer, the protective insulating layer, the first connection pad; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip.

公开(公告)号：US20220020653A1

公开(公告)日：2022-01-20

申请号：US17488662

申请日：2021-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM ,  Taewon YOO

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US20210167054A1

公开(公告)日：2021-06-03

申请号：US16916779

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48

Abstract: Disclosed is a semiconductor package including a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and laterally spaced apart from the first semiconductor chip, a dummy chip on the first semiconductor chip, and a dielectric layer between the first semiconductor chip and the dummy chip. A top surface of the first semiconductor chip may be lower than a top surface of the second semiconductor chip. The dielectric layer may include an inorganic dielectric material.

公开(公告)号：US20230069511A1

公开(公告)日：2023-03-02

申请号：US17834066

申请日：2022-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Inhyo HWANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.

公开(公告)号：US20210066148A1

公开(公告)日：2021-03-04

申请号：US16814455

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM ,  Taewon YOO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

公开(公告)号：US20250105217A1

公开(公告)日：2025-03-27

申请号：US18973467

申请日：2024-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Myungkee CHUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

公开(公告)号：US20220359469A1

公开(公告)日：2022-11-10

申请号：US17578621

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Younglyong KIM ,  Myungkee CHUNG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

公开(公告)号：US20220068887A1

公开(公告)日：2022-03-03

申请号：US17218340

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Myungkee CHUNG ,  Younglyong KIM

IPC: H01L25/065 ,  H01L23/12 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate, a lower package structure on the package substrate that includes a mold substrate, a semiconductor chip in the mold substrate having chip pads exposed through the mold substrate, spacer chips in the mold substrate and spaced apart from the semiconductor chip, and a redistribution wiring layer on the mold substrate that has redistribution wirings electrically connected to the chip pads, first and second stack structures on the lower package structure spaced apart from each other, each of the first and second stack structures including stacked memory chips, and a molding member covering the lower package structure and the first and second stack structures, wherein the mold substrate includes a first covering portion covering side surfaces of the semiconductor chip and the spacer chips, and a second covering portion covering a lower surface of the semiconductor chip.

公开(公告)号：US20240321815A1

公开(公告)日：2024-09-26

申请号：US18735408

申请日：2024-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohyun NAM ,  Younglyong KIM

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32235 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/3512

Abstract: A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.