Abstract:
An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.
Abstract:
A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.
Abstract:
A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.
Abstract:
An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.
Abstract:
A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.
Abstract:
Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.
Abstract:
A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.
Abstract:
A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.
Abstract:
A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
Abstract:
Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.