公开(公告)号：US20190280000A1

公开(公告)日：2019-09-12

申请号：US15914560

申请日：2018-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi Nakamura ,  Kota Funayama

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/10 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02

Abstract: A first alternating stack of first insulating layers and first spacer layers, an inter-tier dielectric layer, a sacrificial memory opening fill structure, and a second alternating stack of second insulating layers and second spacer layers are formed over a substrate. The spacer layers are formed as, or are subsequently replaced with, electrically conductive layers. A concave downward-facing surface of the inter-tier dielectric layer is formed on a convex upper surface of the sacrificial memory opening fill structure. An inter-tier memory opening is provided by forming second-tier memory opening and removing the sacrificial memory opening fill structure. A memory stack structure including a memory film is formed in the inter-tier memory opening. The memory film includes a rounded top surface at the joint between tiers to enhance its reliability.

公开(公告)号：US20240179916A1

公开(公告)日：2024-05-30

申请号：US18221711

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Kota Funayama

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

公开(公告)号：US11444101B2

公开(公告)日：2022-09-13

申请号：US17038870

申请日：2020-09-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jo Sato ,  Kota Funayama ,  Tatsuya Hinoue

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L23/522

Abstract: A lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory stack structures are formed through the alternating stack. Backside openings are formed through the alternating stack and into the in-process source-level material layers such that tapered surfaces are formed through the upper source-level dielectric etch-stop layer. A source cavity is formed by removing the source-level sacrificial layer, and a continuous source contact layer is formed in the source cavity and in peripheral portions of the backside openings. Portions of the continuous source contact layer overlying the tapered surfaces are removed by performing an isotropic etch process. Remaining portions of the continuous source contact layer comprise a source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US11367733B1

公开(公告)日：2022-06-21

申请号：US17113254

申请日：2020-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro Hosoda ,  Masanori Tsutsumi ,  Kota Funayama

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.

公开(公告)号：US20170263642A1

公开(公告)日：2017-09-14

申请号：US15607837

申请日：2017-05-30

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Kota Funayama ,  Toru Miwa ,  Hiroyuki Ogawa

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L28/20

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

公开(公告)号：US11756877B2

公开(公告)日：2023-09-12

申请号：US17155512

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Ohsawa ,  Kota Funayama ,  Hisaya Sakai ,  Yoshitaka Otsu

IPC: H01L23/52 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.

公开(公告)号：US09941297B2

公开(公告)日：2018-04-10

申请号：US15607837

申请日：2017-05-30

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Kota Funayama ,  Toru Miwa ,  Hiroyuki Ogawa

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L28/20

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

公开(公告)号：US20240178140A1

公开(公告)日：2024-05-30

申请号：US18221689

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Kota Funayama

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

公开(公告)号：US10600802B2

公开(公告)日：2020-03-24

申请号：US15914560

申请日：2018-03-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi Nakamura ,  Kota Funayama

IPC: H01L27/11582 ,  H01L29/788 ,  H01L29/10 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/1157

Abstract: A first alternating stack of first insulating layers and first spacer layers, an inter-tier dielectric layer, a sacrificial memory opening fill structure, and a second alternating stack of second insulating layers and second spacer layers are formed over a substrate. The spacer layers are formed as, or are subsequently replaced with, electrically conductive layers. A concave downward-facing surface of the inter-tier dielectric layer is formed on a convex upper surface of the sacrificial memory opening fill structure. An inter-tier memory opening is provided by forming second-tier memory opening and removing the sacrificial memory opening fill structure. A memory stack structure including a memory film is formed in the inter-tier memory opening. The memory film includes a rounded top surface at the joint between tiers to enhance its reliability.

公开(公告)号：US10224240B1

公开(公告)日：2019-03-05

申请号：US15635023

申请日：2017-06-27

Applicant: SANDISK TECHNOLOGIES LLC ,  KABUSHIKI KAISHA TOSHIBA

Inventor： Kota Funayama ,  Masayuki Fukai ,  Takaya Yamanaka ,  Masaki Tsuji ,  Akira Matsumura

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A first tier structure is provided by forming first memory openings through a first alternating stack of first insulating layers and first spacer layers, and by forming sacrificial memory opening fill structures in the first memory openings. A second tier structure is formed over the first tier structure by forming a second alternating stack of second insulating layers and second spacer layers. Second memory openings are formed through the second tier structure in areas of the sacrificial memory opening fill structures. Distortion of the first tier structure and misalignment between the first and second memory openings is reduced or prevented by conducting thermal cycles at a lower temperature for the second tier structure than for the first tier structure.