公开(公告)号：US06750876B1

公开(公告)日：2004-06-15

申请号：US09188996

申请日：1998-11-09

申请人： Sean R. Atsatt ,  William S. Jacobs

发明人： Sean R. Atsatt ,  William S. Jacobs

IPC分类号： G09G500

CPC分类号： H04N5/23293 ,  H04N5/772 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N7/01

摘要： A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.

摘要翻译： 用于数字成像系统的可编程显示控制器具有视频控制寄存器，数据访问控制器和可编程调制器。 可编程显示控制被设计成与诸如数字照相机的数字成像系统一起使用，其具有需要各自不同的控制信号，不同的图像信号调制等的各种显示不同的装置。 视频控制寄存器存储指示要输出的视频信号的类型的视频模式位。 数据访问控制器具有用于请求图像数据并将所请求的图像数据存储在缓冲器中的缓冲器。 可编程调制器响应于视频模式位，从存储在缓冲器中的图像数据产生视频信号。 在一些实施例中，解码器检测并解码所接收的图像数据中的链接码。 地址发生器响应于解码器，并且输出与解码的链接代码对应的链接地址，用于取出存储在链接地址处的图像数据。

公开(公告)号：US09537488B1

公开(公告)日：2017-01-03

申请号：US13105968

申请日：2011-05-12

申请人： Sean R. Atsatt ,  Kent Orthner ,  Daniel R. Mansur

发明人： Sean R. Atsatt ,  Kent Orthner ,  Daniel R. Mansur

IPC分类号： H03K19/0175 ,  H03K19/177

CPC分类号： H03K19/017581 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17748

摘要： An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.

摘要翻译： 现场可编程门阵列（FPGA）包括使用FPGA架构实现的电路。 FPGA还包括实现为硬化电路的另一个电路。 FPGA还包括可配置接口电路，其适于将两个电路耦合在一起。

公开(公告)号：US08467218B1

公开(公告)日：2013-06-18

申请号：US12966391

申请日：2010-12-13

申请人： Sean R. Atsatt ,  Daniel R. Mansur

发明人： Sean R. Atsatt ,  Daniel R. Mansur

IPC分类号： G11C5/06

CPC分类号： G06F13/405

摘要： Various novel aspects are disclosed by reference to an integrated circuit block that includes programmable regions, and extra-block connection pins or points with adapter circuitry, coupled by an interconnect system. Multiple independent interconnects are disclosed within the interconnect system, as are options for the composition of the programmable regions and their connectivity with the interconnect system. Adapter circuitry is disclosed that includes support for coupling extra-block memory circuits or devices using a variety of modes, protocols, and options. Modular circuit blocks provide flexibility at the interface between programmable region and fixed function circuitry.

摘要翻译： 通过参考包括可编程区域的集成电路块和通过互连系统耦合的具有适配器电路的多块连接引脚或点来公开各种新颖的方面。 在互连系统中公开了多个独立互连，以及可编程区域的组合及其与互连系统的连接性的选择。 公开了适配器电路，其包括使用各种模式，协议和选项来耦合额外块存储器电路或设备的支持。 模块化电路块在可编程区域和固定功能电路之间的接口处提供灵活性。

公开(公告)号：US5983309A

公开(公告)日：1999-11-09

申请号：US917005

申请日：1997-08-20

申请人： Sean R. Atsatt ,  Pervez Edul Virjee ,  Prafulla Bollampalli Reddy ,  Mark Hubert Groo ,  Timothy Verne Gates ,  William Kent Weberg ,  Jimmie Ray Shaver

发明人： Sean R. Atsatt ,  Pervez Edul Virjee ,  Prafulla Bollampalli Reddy ,  Mark Hubert Groo ,  Timothy Verne Gates ,  William Kent Weberg ,  Jimmie Ray Shaver

IPC分类号： G06F11/00 ,  G06F12/10

CPC分类号： G11B20/1883 ,  G11B2020/1242 ,  G11B2220/20

摘要： An address translation unit is provided for logical to physical address conversion. In particular, apparatus and method are described for receiving a logical cylinder head sector for a logical block address and converting it into a physical cylinder head sector. If a logical block address is received, it is converted to a physical block address and then the physical block address is converted into a physical cylinder head sector. If a logical cylinder head sector is first received, it is converted into a logical block address, and then the conversion takes place just as it would for an initially received logical block address.

摘要翻译： 提供地址转换单元用于逻辑到物理地址转换。 具体地，描述了用于接收用于逻辑块地址的逻辑气缸盖扇区并将其转换成物理气缸头扇区的装置和方法。 如果接收到逻辑块地址，则将其转换为物理块地址，然后将物理块地址转换为物理磁盘扇区。 如果首先接收到逻辑气缸盖扇区，则将其转换为逻辑块地址，然后进行转换，就像初始接收的逻辑块地址一样。

公开(公告)号：US20210013885A1

公开(公告)日：2021-01-14

申请号：US17033342

申请日：2020-09-25

申请人： Sean R. Atsatt ,  Arun Jangity ,  Thien Le ,  Simon Chong

发明人： Sean R. Atsatt ,  Arun Jangity ,  Thien Le ,  Simon Chong

IPC分类号： H03K19/1776 ,  H03K19/17724 ,  H03K19/17736 ,  H03K3/037

摘要： Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

公开(公告)号：US06192492B1

公开(公告)日：2001-02-20

申请号：US09037468

申请日：1998-03-10

申请人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

发明人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

IPC分类号： H02H305

CPC分类号： G06F11/10 ,  G06F13/385

摘要： An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead. Also disclosed are interface circuitry and a new ATA-compatible transfer mode capable of transferring data at 40 MB/sec, the rate supported by local bus adapters for disk drives. Given the physical limits of the ATA cables and connectors, the error correction and detection features are especially useful for correcting data words corrupted during high-speed transmission; however, error correction and detection can also operate independently of the fast transfer mode. Consistent with full backward compatibility, a hard drive configured with the new, fast, error-correcting interface is transparently functional when plugged into a current ATA adapter provided by a legacy computer system.

摘要翻译： 公开了具有纠错和检测能力的具有ATA的驱动接口。 完全ATA向后兼容，此接口与当前ATA系统使用相同的物理电缆和连接器，采用与早期版本的ATA标准提供的总线驱动器相同或向后兼容的总线驱动器，并使用带有电缆信号转换的信号 比当前ATA设备目前看到的更快。 错误检测功能指示数据块何时在设备和主机之间传输错误; 纠错特征识别错误发送的字，并校正接口侧的这些字。 为了保持ATA向后兼容性，数据完整性检查功能在数据传输中不需要附加字，数据校正功能不需要新的数据传输协议或额外的数据传输开销。 还公开了接口电路和能够以40MB /秒传输数据的新的ATA兼容传输模式，本地总线适配器为磁盘驱动器支持的速率。 鉴于ATA电缆和连接器的物理限制，纠错和检测功能对于纠正在高速传输期间损坏的数据字特别有用; 然而，纠错和检测也可以独立于快速传输模式进行操作。 与完全向后兼容性相一致，配置有新的，快速的错误纠正接口的硬盘驱动器在插入到传统计算机系统提供的当前ATA适配器时是透明的。

公开(公告)号：US5818654A

公开(公告)日：1998-10-06

申请号：US869041

申请日：1997-06-04

申请人： Prafulla B. Reddy ,  Jimmie R. Shaver ,  Sean R. Atsatt ,  Mark H. Groo ,  Timothy V. Gates ,  William K. Weberg

发明人： Prafulla B. Reddy ,  Jimmie R. Shaver ,  Sean R. Atsatt ,  Mark H. Groo ,  Timothy V. Gates ,  William K. Weberg

IPC分类号： G11B20/18 ,  G11B27/30 ,  G11B5/09 ,  G11B5/596

CPC分类号： G11B20/1883 ,  G11B27/3027 ,  G11B2020/1234 ,  G11B2220/20

摘要： A memory medium has a plurality of tracks arranged in a plurality of sectors with each track sector having a format which does not include header fields identifying sectors or sector defects or defect management procedures. Track management apparatus identifies the track sector currently confronting a transducer; the track management being based on sector pulses (in the case of a dedicated servo system), or being calculated based on track information, an index pulse and data wedge information from previous wedges (in the case of embedded servo systems), or being derived from a lookup table. To accommodate sector defects, a defect bank contains the identity and type of each defective or spare sector. Defect management apparatus is connected to the defect bank and track management apparatus to indicate when the sector confronting the transducer is a defective or spare sector to halt data transfer to thereby skip the defective sector, or to generate an interrupt signal to the processor to transfer data between the processor and an alternate sector.

摘要翻译： 存储器介质具有布置在多个扇区中的多个轨道，每个轨道扇区具有不包括标识扇区或扇区缺陷或缺陷管理过程的报头字段的格式。 轨道管理装置识别目前面对换能器的轨道扇区; 轨道管理基于扇区脉冲（在专用伺服系统的情况下），或者基于轨迹信息计算，索引脉冲和来自先前楔形（在嵌入式伺服系统的情况下）的数据楔形信息，或被导出 从查找表。 为了适应部门缺陷，缺陷库包含每个有缺陷或备用扇区的身份和类型。 缺陷管理装置连接到缺陷库和跟踪管理装置，以指示何时面向传感器的扇区是有缺陷的或备用的扇区，以停止数据传输，从而跳过缺陷扇区，或者产生一个中断信号给处理器传送数据 处理器和备用扇区之间。

公开(公告)号：US5784390A

公开(公告)日：1998-07-21

申请号：US491513

申请日：1995-06-19

申请人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

发明人： John C. Masiewicz ,  Sean R. Atsatt ,  Jeffrey Alan Miller

IPC分类号： G06F11/10 ,  G06F13/38 ,  G06F13/42

CPC分类号： G06F11/10 ,  G06F13/385

摘要： An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead. Also disclosed are interface circuitry and a new ATA-compatible transfer mode capable of transferring data at 40 MB/sec, the rate supported by local bus adapters for disk drives. Given the physical limits of the ATA cables and connectors, the error correction and detection features are especially useful for correcting data words corrupted during high-speed transmission; however, error correction and detection can also operate independently of the fast transfer mode. Consistent with full backward compatibility, a hard drive configured with the new, fast, error correcting interface is transparently functional when plugged into a current ATA adapter provided by a legacy computer system.

摘要翻译： 公开了具有纠错和检测能力的具有ATA的驱动接口。 完全ATA向后兼容，此接口与当前ATA系统使用相同的物理电缆和连接器，采用与早期版本的ATA标准提供的总线驱动器相同或向后兼容的总线驱动器，并使用带有电缆信号转换的信号 比当前ATA设备目前看到的更快。 错误检测功能指示数据块何时在设备和主机之间传输错误; 纠错特征识别错误发送的字，并校正接口侧的这些字。 为了保持ATA向后兼容性，数据完整性检查功能在数据传输中不需要附加字，数据校正功能不需要新的数据传输协议或额外的数据传输开销。 还公开了接口电路和能够以40MB /秒传输数据的新的ATA兼容传输模式，本地总线适配器为磁盘驱动器支持的速率。 鉴于ATA电缆和连接器的物理限制，纠错和检测功能对于纠正在高速传输期间损坏的数据字特别有用; 然而，纠错和检测也可以独立于快速传输模式进行操作。 与完全向后兼容性一致，配置有新的，快速的纠错接口的硬盘驱动器在插入到传统计算机系统提供的当前ATA适配器时是透明的。

公开(公告)号：US08166237B1

公开(公告)日：2012-04-24

申请号：US12605222

申请日：2009-10-23

申请人： Sean R. Atsatt ,  Kent Orthner

发明人： Sean R. Atsatt ,  Kent Orthner

IPC分类号： G06F12/00

CPC分类号： G06F13/1642

摘要： A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.

摘要翻译： 可编程逻辑器件包括硬逻辑部分，其选择性地聚合数据端口的带宽并且逻辑地和物理地映射来自这些端口的事务。 存储器接口结构是硬逻辑部分的一部分，其包括随机存取存储器（RAM），复用器和指针，其允许静态或动态带宽配置作为检查使用队列的系统流量的仪器的功能。 该接口允许许多具有多个逻辑线程的启动器在不同的队列模块中共享和使用许多物理线程。

公开(公告)号：US5745793A

公开(公告)日：1998-04-28

申请号：US485965

申请日：1995-06-07

申请人： Sean R. Atsatt ,  John M. Wright

发明人： Sean R. Atsatt ,  John M. Wright

IPC分类号： G06F3/06 ,  G06F5/10 ,  G11B20/10 ,  G11B20/14 ,  G06F13/00

CPC分类号： G06F5/10 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0674 ,  G11B20/10009 ,  G11B20/1403 ,  G11B2020/10666

摘要： Bandwidth optimization between a microprocessor and a disc drive controller. Method and apparatus are disclosed for synchronizing asynchronous microprocessor writes to synchronous read/write channel operation. In this synchronization, bandwidth of the microprocessor is equal to or greater than the bandwidth of the disc controller. Both no ready line and ready line implementations are described.

摘要翻译： 微处理器与磁盘驱动器控制器之间的带宽优化。 公开了用于将异步微处理器写入同步读/写通道操作同步的方法和装置。 在该同步中，微处理器的带宽等于或大于盘控制器的带宽。 描述了没有准备好的线路和就绪线路实现。