Semiconductor device, display device, and electronic appliance
    1.
    发明授权
    Semiconductor device, display device, and electronic appliance 有权
    半导体装置,显示装置和电子设备

    公开(公告)号:US09406808B2

    公开(公告)日:2016-08-02

    申请号:US13671638

    申请日:2012-11-08

    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

    Abstract translation: 在使用氧化物半导体形成沟道形成区域的沟道保护薄膜晶体管中,使用通过热处理脱水或脱氢的氧化物半导体层作为有源层,包括纳米晶体的晶体区域包含在表面 并且其余部分是无定形的或由非晶/非晶体和微晶体的混合物形成,其中非晶区域用微晶点缀。 通过使用具有这种结构的氧化物半导体层,可以防止由于进入水分或从表面部分去除氧气或从表面部分排出而引起的n型变化和产生寄生通道,并且与源极接触电阻 可以减少漏电极。

    Method for manufacturing semiconductor device
    2.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号:US09275875B2

    公开(公告)日:2016-03-01

    申请号:US14529525

    申请日:2014-10-31

    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.

    Abstract translation: 目的在于提供一种具有稳定的电气特性和高可靠性的氧化物半导体的半导体装置。 在包括氧化物半导体层的底栅晶体管的制造工艺中,在氧化物气氛中进行热处理,在真空中进行热处理,依次进行氧化物半导体层的脱水或脱氢。 此外,与热处理同时进行具有短波长的光的照射,由此促进氢,OH等的消除。 包括通过这种热处理进行脱水或脱氢处理的氧化物半导体层的晶体管具有改善的稳定性,从而抑制了由于光照射或偏压温度应力(BT)测试而导致的晶体管的电特性的变化。

    Oxide semiconductor stacked film and semiconductor device
    5.
    发明授权
    Oxide semiconductor stacked film and semiconductor device 有权
    氧化物半导体层叠膜和半导体器件

    公开(公告)号:US09123573B2

    公开(公告)日:2015-09-01

    申请号:US14527076

    申请日:2014-10-29

    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

    Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外,提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟,镓和锌的第一氧化物半导体层,第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比,并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。

    Oxide semiconductor stacked film and semiconductor device
    7.
    发明授权
    Oxide semiconductor stacked film and semiconductor device 有权
    氧化物半导体层叠膜和半导体器件

    公开(公告)号:US09583570B2

    公开(公告)日:2017-02-28

    申请号:US14813408

    申请日:2015-07-30

    Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

    Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外,提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟,镓和锌的第一氧化物半导体层,第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比,并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。

    Lamination system, IC sheet, scroll of IC sheet, and method for manufacturing IC chip

    公开(公告)号:US11188805B2

    公开(公告)日:2021-11-30

    申请号:US16248349

    申请日:2019-01-15

    Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.

Patent Agency Ranking