公开(公告)号：US06473282B1

公开(公告)日：2002-10-29

申请号：US09547186

申请日：2000-04-11

申请人： Shi-Tron Lin ,  Ta-Lee Yu ,  Yung-Chow Peng

发明人： Shi-Tron Lin ,  Ta-Lee Yu ,  Yung-Chow Peng

IPC分类号： H02H320

CPC分类号： H01L27/0251

摘要： A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.

摘要翻译： 公开了一种用于通过第一电力轨道和第二电力轨道供电的集成电路的闩锁保护电路，该集成电路具有至少一个导电类型的半导体本体。 闩锁保护电路包括控制电路和开关电路。 控制电路连接到第一电源轨和第二电源轨，用于检测它们之间的相对电压，并产生第一控制信号和第二控制信号。 开关电路连接到第一电源轨和控制电路。 当相对电压大于第一预定值时，响应于第一控制信号的开关电路将第一电源轨与至少一个半导体块电连接。 当相对电压小于第一预定值时，响应于第一控制信号的开关将第一电力轨与至少一个半导体块电气断开。

公开(公告)号：US5892261A

公开(公告)日：1999-04-06

申请号：US780670

申请日：1997-01-07

申请人： Shi-Tron Lin ,  Ta-Lee Yu ,  Chau Neng Wu ,  Yu Chen Lin ,  Yang Sen Yeh

发明人： Shi-Tron Lin ,  Ta-Lee Yu ,  Chau Neng Wu ,  Yu Chen Lin ,  Yang Sen Yeh

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree. bend therein such that a bitline contact in the corresponding corner portion of the active region is located between the bend and an outer peripheral edge of the corner portion. This layout allows the contact-to-diffusion-edge and contact-to-gate-edge spacings of the VDD contacts to be increased such that internal circuit ESD immunity of the memory device is improved without impacting device dimension and layout area constraints.

摘要翻译： 一种在半导体存储器件中使用的装置和方法，用于减少由于位线上拉电路或其它类型电路上的静电放电（ESD）的影响而产生的内部电路损坏。 存储器件中的多个位线中的每一个与相应的N型MOSFET的源极耦合。 每个源极端子形成在存储器件的至少一个有源区域的单独拐角部分中，并且经由布置在拐角部分中的位线接触件耦合到给定的位线。 N型MOSFET的每个漏极端子由有源区域的另一部分形成，并通过VDD触点耦合到存储器件的VDD电源。 给定MOSFET的栅极端子由覆盖有源区域中的沟道的多晶硅栅极区域形成。 栅极区域在其中具有大约90度的弯曲，使得有源区域的相应拐角部分中的位线接触位于弯曲部分和拐角部分的外周边缘之间。 该布局允许增加VDD触点的接触到扩散边缘和接触到栅极边缘间隔，使得存储器件的内部电路ESD抗扰度得到改善，而不会影响器件尺寸和布局面积限制。

公开(公告)号：US6157070A

公开(公告)日：2000-12-05

申请号：US27533

申请日：1998-02-23

申请人： Shi-Tron Lin ,  Ta-Lee Yu

发明人： Shi-Tron Lin ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L29/76 ,  H01L27/10 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0921 ,  H01L27/0266

摘要： In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

摘要翻译： 在多电源CMOS IC中，如果在上电期间VDDH施加得比VDDL慢，则通常反向偏置的一些扩散结可能会瞬间变为正向偏置，并产生闭锁以产生对电路的永久性损坏。 因此，提供了防止在多电源IC中闭锁的保护电路。 保护电路包括一个N沟道MOSFET，其栅极连接到高电压总线，其漏极连接到低压电源，其源极连接到低压母线以控制上电顺序 高电压和低电压的多电源IC，并防止闩锁。 N沟道MOSFET可以具有不同的模式，例如具有低阈值电压的增强模式，耗尽模式或增强模式。

公开(公告)号：US06542346B1

公开(公告)日：2003-04-01

申请号：US09586568

申请日：2000-06-02

申请人： Wei-Fan Chen ,  Shu-Chuan Lee ,  Ta-Lee Yu ,  Shi-Tron Lin

发明人： Wei-Fan Chen ,  Shu-Chuan Lee ,  Ta-Lee Yu ,  Shi-Tron Lin

IPC分类号： H02H322

CPC分类号： H01L27/0251 ,  H01L29/7436 ,  H01L29/87

摘要： A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.

摘要翻译： 连接到集成电路的焊盘的高压公差输入缓冲器和高压ESD保护电路，用于防止快速栅极氧化物老化。 本发明的高电压公差输入缓冲器包括电压共享电路和开关电路，其中电压共享电路连接在焊盘和电源轨之间，并产生不高于焊盘电压的参考电压 。 开关电路连接到分压电路，并包括控制栅极，以根据参考电压来控制开关电路的开关操作。 本发明可以实现以解决快速栅极氧化物老化问题，而不会通过采用电压共享电路而引起原始工艺流程的任何变化。

公开(公告)号：US20070268046A1

公开(公告)日：2007-11-22

申请号：US11754957

申请日：2007-05-29

申请人： Ta-Lee Yu ,  Lei Wang ,  Li Da

发明人： Ta-Lee Yu ,  Lei Wang ,  Li Da

IPC分类号： H03K3/00

CPC分类号： H03K19/003

摘要： A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

摘要翻译： 一种用于控制输入/输出驱动器的系统和方法。 该系统包括被配置为接收第一电源电压和第二电源电压并产生控制信号的控制系统，以及包括第一门，第一终端和第二终端的第一晶体管。 第一栅极被配置为接收控制信号，并且第一端子被配置为接收第一电源电压。 另外，该系统包括包括第二栅极，第三端子和第四端子的第二晶体管，并且第二栅极耦合到第二端子。 此外，该系统包括包括第三栅极，第五端子和第六端子的第三晶体管，并且第三栅极被配置为接收控制信号。 此外，该系统包括耦合到第四端子和第五端子的输入/输出焊盘。

公开(公告)号：US06872987B2

公开(公告)日：2005-03-29

申请号：US10462287

申请日：2003-06-16

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L21/332 ,  H01L27/02 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7436 ,  H01L27/0259 ,  H01L29/66121 ,  H01L29/66393 ,  H01L29/87

摘要： A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

摘要翻译： 对于与浅沟槽隔离结构一起使用的SCR ESD保护器件，描述了一种新颖的器件结构和工艺。 本发明结合了跨越SCR二极管结元件的多晶硅栅极以及SCR元件和相邻STI结构之间的桥接。 有战略地定位的多晶硅栅极的存在有效地抵消了非平面STI“下拉”区域的有害影响，以及补偿硅化物结构与由STI元件限制的二极管元件的有效结深度的相互作用。 将栅极连接到适当的电压源，例如通常接地的SCR阳极输入电压和SCR阴极电压，可以降低ESD保护器件的正常工作泄漏。

公开(公告)号：US06555458B1

公开(公告)日：2003-04-29

申请号：US10046802

申请日：2002-01-14

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical metal fuse for use with a semiconductor integrated circuit device. At least two varying trench metal depths may be formed on a substrate to configure the electrical metal fuse thereon. Additionally, at least two different widths of single metal lines, may be configured on the substrate. As a result of the two different trench depths and two different widths of metal formed thereon to create the electrical metal fuse, increases in current density gradients and thermal gradients thereof can be generated. The trench metal depths and width of metal are formed from copper. The electrical metal fuse generally comprises a current density ratio greater than 10 to 1.

摘要翻译： 一种用于形成用于半导体集成电路器件的电金属熔丝的方法。 可以在衬底上形成至少两个变化的沟槽金属深度以在其上配置电金属熔丝。 另外，可以在衬底上配置至少两个不同宽度的单个金属线。 由于两个不同的沟槽深度和两个不同宽度的金属形成在其上以产生电金属熔断器，所以可以产生电流密度梯度和其热梯度的增加。 金属的沟槽金属深度和宽度由铜形成。 电气金属保险丝通常包括大于10比1的电流密度比。

公开(公告)号：US06353237B1

公开(公告)日：2002-03-05

申请号：US09365431

申请日：1999-08-02

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2974

CPC分类号： H01L27/0262 ,  H01L27/0255

摘要： The present invention provides an ESD protection circuit having at least one semiconductor-controlled rectifier and a diode. The SCR having a floating anode gate is connected between a first circuit node a second circuit node. The diode is connected between an anode and a cathode gate of the SCR to activate the SCR so that a potential between the first circuit node and second circuit node can be clamped at about a holding voltage of the SCR during an ESD event.

摘要翻译： 本发明提供一种具有至少一个半导体可控整流器和二极管的ESD保护电路。 具有浮动阳极栅极的SCR连接在第一电路节点和第二电路节点之间。 二极管连接在SCR的阳极和阴极栅之间，以激活SCR，使得在ESD事件期间，第一电路节点和第二电路节点之间的电位可以在SCR的约保持电压处被钳位。

公开(公告)号：US06329223B2

公开(公告)日：2001-12-11

申请号：US09784145

申请日：2001-02-16

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/45099 ,  H01L2924/00

摘要： An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

摘要翻译： 集成电路封装包括半导体芯片，多个有线引脚和至少一个非有线引脚。 无线引脚的尺寸被最小化，或者无线引脚被消除，以便增加引脚间距。 引脚间距的增加防止了由于非接线引脚的静电应力引起的集成电路封装中的静电放电故障。

公开(公告)号：US06297536B2

公开(公告)日：2001-10-02

申请号：US09270830

申请日：1999-03-18

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L3300

CPC分类号： H01L27/0814 ,  H01L27/0255 ,  H01L29/8611

摘要： A diode structure compatible with silicide processes for electrostatic discharge protection is disclosed. The diode structure comprises a semiconductor layer of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor layer, and a doped region of the second conductivity type formed in the semiconductor layer around the diffusion region. The doped region has a doping concentration less than that of the diffusion region to provide a ballastic resistance under a high current stressing condition.

摘要翻译： 公开了一种与用于静电放电保护的硅化物工艺兼容的二极管结构。 二极管结构包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的扩散区和形成在扩散区周围的半导体层中的第二导电类型的掺杂区。 掺杂区域的掺杂浓度小于扩散区域的掺杂浓度，以在高电流应力条件下提供抗弹性电阻。