公开(公告)号：US12199047B2

公开(公告)日：2025-01-14

申请号：US17572001

申请日：2022-01-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Po-Yuan Su

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/58 ,  H01L23/42 ,  H05K1/02

Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

公开(公告)号：US20240038685A1

公开(公告)日：2024-02-01

申请号：US17950914

申请日：2022-09-22

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Fang-Lin Tsai

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L24/32 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L21/4817 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16235

Abstract: An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.

公开(公告)号：US09972564B2

公开(公告)日：2018-05-15

申请号：US14290217

申请日：2014-05-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L23/498 ,  H01L29/78 ,  H01L21/265 ,  H01L29/762 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/26533 ,  H01L21/486 ,  H01L29/762 ,  H01L29/7834 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

公开(公告)号：US12051641B2

公开(公告)日：2024-07-30

申请号：US17527434

申请日：2021-11-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Cheng-Yu Kang ,  Yu-Po Wang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2924/3511

Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

公开(公告)号：US20230282586A1

公开(公告)日：2023-09-07

申请号：US17740796

申请日：2022-05-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Shuai-Lin Liu

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L25/105 ,  H01L23/481 ,  H01L25/50 ,  H01L23/5386 ,  H01L24/16

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

公开(公告)号：US20150206814A1

公开(公告)日：2015-07-23

申请号：US14290217

申请日：2014-05-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L23/14 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/26533 ,  H01L21/486 ,  H01L29/762 ,  H01L29/7834 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

Abstract translation: 提供一种用于安装半导体器件的层结构的制造方法，其包括以下步骤：提供基材，其中所述基材具有导电层，所述导电层具有第一表面，所述第一表面具有多个第一导电元件和相对的第二表面 具有多个第二导电元件，以及第一密封剂，其形成在所述导电层的第一表面上，用于封装所述第一导电元件; 部分去除所述导电层以形成电连接所述第一导电元件和所述第二导电元件的电路层; 以及在所述第一密封剂的底表面上形成用于封装所述电路层和所述第二导电元件的第二密封剂，从而降低制造难度并提高产品产率。

公开(公告)号：US20230378072A1

公开(公告)日：2023-11-23

申请号：US17857887

申请日：2022-07-05

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Shuai-Lin Liu ,  Nai-Hao Kao ,  Chao-Chiang Pu ,  Yi-Min Fu ,  Yu-Po Wang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L24/16

Abstract: An electronic package is provided, in which a plurality of electronic elements are disposed on a plurality of carrier structures, and at least one bridging element is disposed between at least two of the carrier structures to electrically bridge the two carrier structures. Therefore, when there is a need to increase the function of the electronic package, only one electronic element is arranged on a single carrier structure, and there is no need to increase the panel area of the carrier structure, so as to facilitate the control of the panel area of the carrier structure and avoid warpage of the carrier structure due to the oversized panel.

公开(公告)号：US20220399246A1

公开(公告)日：2022-12-15

申请号：US17829533

申请日：2022-06-01

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yi-Min Fu ,  Chi-Ching Ho ,  Yu-Po Wang

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.

公开(公告)号：US10396021B2

公开(公告)日：2019-08-27

申请号：US15950734

申请日：2018-04-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L21/48 ,  H01L29/78 ,  H01L21/265 ,  H01L23/498 ,  H01L29/762

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

公开(公告)号：US12176291B2

公开(公告)日：2024-12-24

申请号：US17740796

申请日：2022-05-10

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chao-Chiang Pu ,  Chi-Ching Ho ,  Yi-Min Fu ,  Yu-Po Wang ,  Shuai-Lin Liu

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.