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公开(公告)号：US20240038685A1
公开(公告)日：2024-02-01
申请号：US17950914
申请日：2022-09-22
发明人： Chao-Chiang Pu , Chi-Ching Ho , Yi-Min Fu , Yu-Po Wang , Fang-Lin Tsai
IPC分类号： H01L23/00 , H01L25/10 , H01L23/498 , H01L23/538 , H01L21/48
CPC分类号： H01L23/562 , H01L24/16 , H01L24/73 , H01L24/32 , H01L25/105 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/5381 , H01L23/5385 , H01L23/5386 , H01L21/4817 , H01L2924/37001 , H01L2924/3511 , H01L2224/73204 , H01L2224/32225 , H01L2224/16227 , H01L2224/16238 , H01L2224/16235
摘要： An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.
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公开(公告)号：US10236261B2
公开(公告)日：2019-03-19
申请号：US15492394
申请日：2017-04-20
发明人： Fang-Lin Tsai , Yi-Feng Chang , Lung-Yuan Wang
IPC分类号： H01L23/552 , H01L21/48 , H01L21/56 , H01L21/52 , H01L23/31 , H01L23/16 , H01L25/065 , H01L25/00 , H01L23/00
摘要： An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.
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公开(公告)号：US09972564B2
公开(公告)日：2018-05-15
申请号：US14290217
申请日：2014-05-29
发明人： Fang-Lin Tsai , Yi-Feng Chang , Cheng-Jen Liu , Yi-Min Fu , Hung-Chi Chen
IPC分类号： H01L23/498 , H01L29/78 , H01L21/265 , H01L29/762 , H01L21/48
CPC分类号： H01L23/49827 , H01L21/26533 , H01L21/486 , H01L29/762 , H01L29/7834 , H01L2224/16225 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
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公开(公告)号：US20220148996A1
公开(公告)日：2022-05-12
申请号：US17135161
申请日：2020-12-28
发明人： Fang-Lin Tsai , Chia-Yu Kuo , Pei-Geng Weng , Wei-Son Tsai , Yih-Jenn Jiang
摘要： An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
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公开(公告)号：US20180233442A1
公开(公告)日：2018-08-16
申请号：US15950734
申请日：2018-04-11
发明人： Fang-Lin Tsai , Yi-Feng Chang , Cheng-Jen Liu , Yi-Min Fu , Hung-Chi Chen
IPC分类号： H01L23/498 , H01L21/265 , H01L29/78 , H01L29/762 , H01L21/48
CPC分类号： H01L23/49827 , H01L21/26533 , H01L21/486 , H01L29/762 , H01L29/7834 , H01L2224/16225 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
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公开(公告)号：US20180211925A1
公开(公告)日：2018-07-26
申请号：US15492394
申请日：2017-04-20
发明人： Fang-Lin Tsai , Yi-Feng Chang , Lung-Yuan Wang
IPC分类号： H01L23/552 , H01L23/31 , H01L25/065 , H01L21/56 , H01L21/48 , H01L21/78 , H01L21/52 , H01L25/00
CPC分类号： H01L23/552 , H01L21/4817 , H01L21/52 , H01L21/561 , H01L21/563 , H01L23/16 , H01L23/3128 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/15311 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012 , H01L2224/85 , H01L2224/81 , H01L2924/014
摘要： An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.
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7.发明申请LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权用于安装半导体器件的层结构及其制造方法公开(公告)号：US20150206814A1
公开(公告)日：2015-07-23
申请号：US14290217
申请日：2014-05-29
发明人： Fang-Lin Tsai , Yi-Feng Chang , Cheng-Jen Liu , Yi-Min Fu , Hung-Chi Chen
CPC分类号： H01L23/49827 , H01L21/26533 , H01L21/486 , H01L29/762 , H01L29/7834 , H01L2224/16225 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
摘要翻译： 提供一种用于安装半导体器件的层结构的制造方法，其包括以下步骤：提供基材，其中所述基材具有导电层，所述导电层具有第一表面，所述第一表面具有多个第一导电元件和相对的第二表面 具有多个第二导电元件，以及第一密封剂，其形成在所述导电层的第一表面上，用于封装所述第一导电元件; 部分去除所述导电层以形成电连接所述第一导电元件和所述第二导电元件的电路层; 以及在所述第一密封剂的底表面上形成用于封装所述电路层和所述第二导电元件的第二密封剂，从而降低制造难度并提高产品产率。
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公开(公告)号：US11791300B2
公开(公告)日：2023-10-17
申请号：US17135161
申请日：2020-12-28
发明人： Fang-Lin Tsai , Chia-Yu Kuo , Pei-Geng Weng , Wei-Son Tsai , Yih-Jenn Jiang
CPC分类号： H01L24/20 , H01L23/3157 , H01L2224/211 , H01L2224/2101 , H01L2224/214 , H01L2224/2105 , H01L2924/3511
摘要： An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
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公开(公告)号：US20230066456A1
公开(公告)日：2023-03-02
申请号：US17840082
申请日：2022-06-14
发明人： Pei-Geng Weng , Fang-Lin Tsai , Wei-Son Tsai , Yih-Jenn Jiang
IPC分类号： H01L23/498
摘要： A substrate structure is provided with a first electrical contact pad formed on an insulating layer of a substrate body, where the first electrical contact pad includes a first pad portion disposed on the insulating layer and at least one first protruding portion embedded in the insulating layer, so that the first pad portion is electrically connected to a circuit layer in the insulating layer by a conductive blind via, and the first protruding portion is free from being electrically connected to the circuit layer, such that, through a design of the first protruding portion, all surfaces of a metal layer formed on the insulating layer can meet the requirement of coplanarity.
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公开(公告)号：US10396021B2
公开(公告)日：2019-08-27
申请号：US15950734
申请日：2018-04-11
发明人： Fang-Lin Tsai , Yi-Feng Chang , Cheng-Jen Liu , Yi-Min Fu , Hung-Chi Chen
IPC分类号： H01L21/48 , H01L29/78 , H01L21/265 , H01L23/498 , H01L29/762
摘要： A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
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