公开(公告)号：US06281081B1

公开(公告)日：2001-08-28

申请号：US09192042

申请日：1998-11-13

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

摘要翻译： 当掺杂NMOS器件的源/漏区时，用于制造浅沟槽隔离结构的离子注入方法将磷离子代替砷离子代入衬底。 或者，在离子注入中使用低能离子来形成NMOS器件的源/漏区。 因此，衬底内的晶体结构的晶格位错减少，并且不需要器件漏电流。

公开(公告)号：US06284647B1

公开(公告)日：2001-09-04

申请号：US09216022

申请日：1998-12-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L214163

CPC分类号： H01L21/76229 ,  Y10S438/926

摘要： A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

摘要翻译： 提供了增强化学机械抛光均匀性的方法。 在浅沟槽隔离结构的制造中，在芯片中形成不同积分的有源区域。 通过程序分析，根据电路设计计算芯片中有源区域的积分。 集成度最高的有源区域之一被用作基础，在其他有源区域中形成虚拟台面以调整芯片的集成。

公开(公告)号：US06200880B1

公开(公告)日：2001-03-13

申请号：US09192877

申请日：1998-11-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

摘要翻译： 提供了用于形成用于隔离器件的浅沟槽隔离的方法。 衬底氧化物和掩模层形成在衬底上并被图案化。 在图案化区域之下的衬底内形成沟槽，并且沟槽填充绝缘体以形成绝缘插头，其是浅沟槽隔离。 在整个基板表面上形成介电层以覆盖器件区域和绝缘插头。

公开(公告)号：US06368971B2

公开(公告)日：2002-04-09

申请号：US09348408

申请日：1999-07-07

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Wei-Wu Liao

IPC分类号： H01L21302

CPC分类号： H01L28/91 ,  H01L27/10814

摘要： A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed. The remaining fifth dielectric layer and the fourth dielectric layer are removed.

摘要翻译： 一种制造电容器的底部电极的方法。 衬底具有形成在其上的接触焊盘，在接触焊盘上形成第一电介质层，并且节点接触件穿过第一电介质层并电耦合到接触焊盘。 在第一电介质层和节点接触件上形成第二电介质层。 在第二电介质层上形成第三电介质层。 在第三电介质层上形成第四电介质层。 形成沟槽以穿透第四，第三和第二介电层并暴露节点接触的表面。 在第四电介质层和沟槽的侧壁和底部上形成导电层。 在导电层上形成第五电介质层，其中第五介电层填充沟槽。 去除第五电介质层的一部分和导电层的一部分直到暴露第四电介质层的表面。 去除剩余的第五电介质层和第四电介质层。

公开(公告)号：US06613655B2

公开(公告)日：2003-09-02

申请号：US10050258

申请日：2002-01-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2122

CPC分类号： H01L27/0617 ,  H01L27/105 ,  H01L27/1052

摘要： A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device region and a hybrid circuit region. A dielectric layer is formed on the peripheral circuit region. A cap layer and a conductive layer are further formed on the polysilicon layer in the memory cell region and on the dielectric layer in the peripheral circuit region. Using the dielectric layer in the peripheral circuit region and the gate oxide layer in the memory cell region as etch stop, the cap layer and the conductive layer in the peripheral circuit region, and the cap layer, the conductive layer and the polysilicon layer are patterned. As a result, at least a gate and a top electrode are formed in the memory cell region and the hybrid circuit region, respectively. Using the gate oxide layer in the peripheral circuit region as an etch stop, the dielectric layer and the conductive layer in the peripheral circuit region are patterned to form a gate in the logic circuit region and the hybrid circuit region, respectively.

摘要翻译： 一种在芯片器件上制造系统的方法。 在具有存储单元区域和外围电路区域的基板上形成栅氧化层和多晶硅层。 外围电路区域还可以分为逻辑器件区域和混合电路区域。 在外围电路区域上形成介电层。 在存储单元区域的多晶硅层和外围电路区域中的电介质层上还形成有盖层和导电层。 使用外围电路区域中的电介质层和存储单元区域中的栅极氧化物层作为蚀刻停止层，外围电路区域中的覆盖层和导电层以及覆盖层，导电层和多晶硅层被图案化 。 结果，至少在存储单元区域和混合电路区域中分别形成栅极和顶部电极。 使用外围电路区域中的栅极氧化层作为蚀刻停止层，对外围电路区域中的电介质层和导电层进行图案化，以分别在逻辑电路区域和混合电路区域中形成栅极。

公开(公告)号：US06468919B2

公开(公告)日：2002-10-22

申请号：US09764326

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2100

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention provides a method to make a local interconnect in an embedded memory. The method first involves defining both a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. A silicon nitride layer and a dielectric layer are then formed, respectively, on the surface of the semiconductor wafer and on each gate. Next, a plurality of landing via holes and local interconnect holes are separately formed in the dielectric layer in the memory array area and in the periphery circuit area, followed by the filling of an electrical conducting layer in each hole to simultaneously form a landing via and local interconnect. Then, the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer on either side of each gate in the periphery circuit area. Finally, a silicide layer is formed on the top surface of the landing via in the memory array area, as well as on the surfaces of each gate and on the surface of the local interconnect in the periphery circuit area.

公开(公告)号：US6007953A

公开(公告)日：1999-12-28

申请号：US98249

申请日：1998-06-16

申请人： Tzung-Han Lee ,  Chi-Fa Ku ,  Army Chung ,  Chien-Li Kuo

发明人： Tzung-Han Lee ,  Chi-Fa Ku ,  Army Chung ,  Chien-Li Kuo

IPC分类号： G03F7/20 ,  H01L23/544 ,  G03F9/00

CPC分类号： H01L23/544 ,  G03F7/2028 ,  H01L2223/54453 ,  H01L2924/0002

摘要： The invention provides a method of avoiding peeling on the wafer edge and the mark number. The method uses a design rule to expose the multi-layer on a wafer. The limit and the scope of the exposed distance are taken to ensure the polysilicon layers and the metal layers are covered by the dielectric layer after exposure. The polysilicon layers or the metal layers don't unclothe from the overlarge distance at the exposed dielectric layer, so the next structure formed on the exposed dielectric layer doesn't peeling from contacting with the polysilicon layer or the metal layer. The invention avoids to contaminate the wafer and the machine after the particles forming from peeling.

摘要翻译： 本发明提供一种避免晶片边缘剥离和标记号的方法。 该方法使用设计规则在晶片上暴露多层。 采取暴露距离的极限和范围来确保暴露后多晶硅层和金属层被电介质层覆盖。 多晶硅层或金属层不会从暴露的电介质层的较大距离脱落，因此在暴露的电介质层上形成的下一个结构不会与多晶硅层或金属层接触而剥离。 本发明避免了在从剥离形成颗粒之后污染晶片和机器。

公开(公告)号：US08692359B2

公开(公告)日：2014-04-08

申请号：US13309559

申请日：2011-12-02

申请人： Yung-Chang Lin ,  Chien-Li Kuo ,  Ming-Tse Lin ,  Sun-Chieh Chien

发明人： Yung-Chang Lin ,  Chien-Li Kuo ,  Ming-Tse Lin ,  Sun-Chieh Chien

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/76232 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.

摘要翻译： 制造半导体器件的方法包括以下步骤。 提供了具有面向第一面的第一面和第二面的半导体衬底。 至少一个开口设置在第一侧限定的保护区域的半导体衬底中。 在第一侧和第二侧上形成第一材料层，第一材料层部分地填充开口。 随后，去除第一侧的第一材料层和保护区域外部的一部分。 在第一侧和第二侧上形成第二材料层，并且第二材料层填充开口。 然后，去除保护区域的第一侧和外侧的第二材料层的一部分。 最后，剩余的第一材料层和第一侧的剩余的第二材料层被平坦化。

公开(公告)号：US20130140708A1

公开(公告)日：2013-06-06

申请号：US13309559

申请日：2011-12-02

申请人： Yung-Chang Lin ,  Chien-Li Kuo ,  Ming-Tse Lin ,  Sun-Chieh Chien

发明人： Yung-Chang Lin ,  Chien-Li Kuo ,  Ming-Tse Lin ,  Sun-Chieh Chien

IPC分类号： H01L23/498 ,  H01L21/76

CPC分类号： H01L21/76898 ,  H01L21/76232 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes the following steps. A semiconductor substrate having a first side and a second side facing to the first side is provided. At least an opening is disposed in the semiconductor substrate of a protection region defined in the first side. A first material layer is formed on the first side and the second side, and the first material layer partially fills the opening. Subsequently, a part of the first material layer on the first side and outside the protection region is removed. A second material layer is formed on the first side and the second side, and the second material layer fills the opening. Then, a part of the second material layer on the first side and outside the protection region is removed. Finally, the remaining first material layer and the remaining second material layer on the first side are planarized.

摘要翻译： 制造半导体器件的方法包括以下步骤。 提供了具有面向第一面的第一面和第二面的半导体衬底。 至少一个开口设置在第一侧限定的保护区域的半导体衬底中。 在第一侧和第二侧上形成第一材料层，第一材料层部分地填充开口。 随后，去除第一侧的第一材料层和保护区域外部的一部分。 在第一侧和第二侧上形成第二材料层，并且第二材料层填充开口。 然后，去除保护区域的第一侧和外侧的第二材料层的一部分。 最后，剩余的第一材料层和第一侧的剩余的第二材料层被平坦化。

公开(公告)号：US07332392B2

公开(公告)日：2008-02-19

申请号：US11279254

申请日：2006-04-11

申请人： Yung-Chang Lin ,  Sun-Chieh Chien ,  Chien-Li Kuo ,  Ruey-Chyr Lee

发明人： Yung-Chang Lin ,  Sun-Chieh Chien ,  Chien-Li Kuo ,  Ruey-Chyr Lee

IPC分类号： H01L21/8242

CPC分类号： H01L29/945 ,  H01L27/1087 ,  H01L29/66181

摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.

摘要翻译： 沟槽电容器结构包括其上包括STI结构的半导体衬底。 电容器深沟槽被蚀刻到半导体衬底中。 环状氧化物层设置在电容器深沟槽的内表面上。 第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。 在第一掺杂多晶硅层上形成电容器电介质层。 第二掺杂多晶硅层形成在电容器介电层上。 在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。 在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。