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    METHODS AND APPARATUS TO REDUCE ERROR IN OPERATIONAL AMPLIFIERS
    1.
    发明公开
    METHODS AND APPARATUS TO REDUCE ERROR IN OPERATIONAL AMPLIFIERS 审中-公开

    公开(公告)号：US20230308055A1

    公开(公告)日：2023-09-28

    申请号：US17897958

    申请日：2022-08-29

    Applicant: Texas Instruments Incorporated

    Inventor： Kunal Karanjkar ,  Venkata Ramanan R ,  Srinivasa BS Chakravarthy ,  Per Torstein Roine

    IPC: H03F1/26 ,  H03F1/30

    CPC classification number: H03F1/26 ,  H03F1/304 ,  H03F2200/375

    Abstract: An example device includes: switch circuitry configured to: connect, in a first state based on a control signal, a first switch input to a first switch output and a second switch input to a second switch output; and connect, in a second state based on the control signal, the first switch input to the second switch output and the second switch input to the first switch output; an operational amplifier configured to: generate, in response to the control signal, a first voltage based on a gain and the connections in the first state; and generate, in response to the control signal, a second voltage based on the gain and the connections in the second state; and an Analog to Digital Converter (ADC) configured to convert the first voltage and the second voltage into a digital value based on a multiplication of the input voltage and the gain.

    Circuit and method for generating a reference voltage with a voltage regulator and a sample and hold circuit
    4.
    发明授权
    Circuit and method for generating a reference voltage with a voltage regulator and a sample and hold circuit 有权

    公开(公告)号：US10719096B2

    公开(公告)日：2020-07-21

    申请号：US15248888

    申请日：2016-08-26

    Applicant: Texas Instruments Incorporated

    Inventor： James Murdock ,  Danielle Griffith ,  Per Torstein Roine

    IPC: G05F1/575 ,  G11C5/14 ,  G11C27/02

    Abstract: A reference generator provides a reference output voltage that is continuously available while providing certain efficiencies of a duty-cycled voltage regulator. The reference output voltage is generated by a sample-and-hold circuit that is coupled to a voltage regulator. On command, the sample-and-hold circuit samples a low dropout voltage regulator that may be referenced by a bandgap circuit. During hold periods of the sample-and-hold circuit, the voltage regulator, in particular the bandgap circuit, may be disabled in order to conserve power. A sample cycle by the sample-and-hold circuit may be triggered by a signal received from a configurable finite state machine. The reference generator is effectively duty cycled in a manner that conserves available battery power, while still providing a constant reference output that is always available. The reference generator is especially suited for low-power, battery operated applications.

    CIRCUITS AND METHODS FOR PERFORMANCE OPTIMIZATION OF SRAM MEMORY
    6.
    发明申请
    CIRCUITS AND METHODS FOR PERFORMANCE OPTIMIZATION OF SRAM MEMORY 有权
    SRAM存储器性能优化的电路和方法

    公开(公告)号：US20160163379A1

    公开(公告)日：2016-06-09

    申请号：US14562056

    申请日：2014-12-05

    Applicant: Texas Instruments Incorporated

    Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

    Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

    Abstract translation: 在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位 沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压， 预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控​​制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电 将被执行。

    RC Oscillator
    7.
    发明申请
    RC Oscillator 有权
    RC振荡器

    公开(公告)号：US20140327486A1

    公开(公告)日：2014-11-06

    申请号：US13887434

    申请日：2013-05-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Per Torstein Roine ,  Danielle L. Griffith ,  Ryan A. Smith

    IPC: H03B5/12

    CPC classification number: H03B5/24 ,  H03K3/03 ,  H03K3/0315 ,  H03K3/354 ,  H03L7/099

    Abstract: In an electronic device, an RC oscillator generally includes a resistor, a capacitor and at least one inverter. The resistor and capacitor generate a time-varying voltage. The time-varying voltage is provided to the at least one inverter to cause a clock signal to propagate therethrough. The clock signal propagates with a time delay that is at least partially dependent on a supply voltage. The supply voltage is adjusted to maintain the time delay at almost a constant value.

    Abstract translation: 在电子设备中，RC振荡器通常包括电阻器，电容器和至少一个逆变器。 电阻和电容产生时变电压。 时变电压被提供给至少一个逆变器以使时钟信号传播通过。 时钟信号以至少部分取决于电源电压的时间延迟传播。 调整电源电压以将时间延迟保持在几乎恒定的值。

    Synchronization of a clock generator divider setting and multiple independent component clock divider settings
    8.
    发明授权
    Synchronization of a clock generator divider setting and multiple independent component clock divider settings 有权

    公开(公告)号：US12045083B2

    公开(公告)日：2024-07-23

    申请号：US18240052

    申请日：2023-08-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Atul Ramakant Lele ,  Per Torstein Roine

    IPC: G06F1/12 ,  G06F1/06 ,  H04J3/06

    CPC classification number: G06F1/12 ,  G06F1/06 ,  H04J3/0679

    Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

    Oscillator closed loop frequency control
    10.
    发明授权
    Oscillator closed loop frequency control 有权

    公开(公告)号：US11496140B2

    公开(公告)日：2022-11-08

    申请号：US17176329

    申请日：2021-02-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Per Torstein Roine ,  Danielle Lyn Griffith

    IPC: H03L7/099 ,  H03K3/03

    Abstract: An electronic device comprises a regulator, and an oscillator and a resistor coupled to the regulator. The electronic device further comprises a feedback controller that includes a differential amplifier coupled between the oscillator, the resistor, and the regulator. The feedback controller is configured to apply a control voltage to the regulator in response to a resistor voltage upon the resistor and an oscillator voltage upon the oscillator. The feedback controller can be coupled to control a substantially equal voltage upon the resistor and the oscillator.

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