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公开(公告)号:US12266579B2
公开(公告)日:2025-04-01
申请号:US17461004
申请日:2021-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Chan Li , Sheng-Chau Chen , Cheng-Hsien Chou , Cheng-Yuan Tsai
Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.
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公开(公告)号:US11869916B2
公开(公告)日:2024-01-09
申请号:US17097360
申请日:2020-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chin-Wei Liang , Sheng-Chau Chen , Hsun-Chung Kuang , Sheng-Chan Li
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/1462 , H01L27/14685 , H01L27/14698
Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.
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公开(公告)号:US11705360B2
公开(公告)日:2023-07-18
申请号:US17197330
申请日:2021-03-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Hsien Chou , Sheng-Chau Chen , Tzu-Jui Wang , Sheng-Chan Li
IPC: H01L21/762 , H01L27/146
CPC classification number: H01L21/76224 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14685
Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.
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公开(公告)号:US20220238568A1
公开(公告)日:2022-07-28
申请号:US17336852
申请日:2021-06-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC: H01L27/146
Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
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公开(公告)号:US20220223634A1
公开(公告)日:2022-07-14
申请号:US17144757
申请日:2021-01-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Che Wei Yang , Sheng-Chan Li , Tsun-Kai Tsao , Chih-Cheng Shih , Sheng-Chau Chen , Cheng-Yuan Tsai
IPC: H01L27/146
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
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公开(公告)号:US11335817B2
公开(公告)日:2022-05-17
申请号:US16845005
申请日:2020-04-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Cheng-Han Lin , Chao-Ching Chang , Yi-Ming Lin , Yen-Ting Chou , Yen-Chang Chen , Sheng-Chan Li , Cheng-Hsien Chou
IPC: H01L31/0216 , H01L31/18 , H01L27/146 , H01L31/0232
Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
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公开(公告)号:US10998364B2
公开(公告)日:2021-05-04
申请号:US16405132
申请日:2019-05-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Chan Li , Cheng-Hsien Chou , Cheng-Yuan Tsai , Keng-Yu Chou , Yeur-Luen Tu
IPC: H01L27/146
Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes an image sensing element arranged within a substrate. One or more isolation structures are arranged within one or more trenches disposed on opposing sides of the image sensing element. The one or more isolation structures extend from a first surface of the substrate to within the substrate. The one or more isolation structures respectively include a reflective element configured to reflect electromagnetic radiation.
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公开(公告)号:US20190259797A1
公开(公告)日:2019-08-22
申请号:US16405132
申请日:2019-05-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Chan Li , Cheng-Hsien Chou , Cheng-Yuan Tsai , Keng-Yu Chou , Yeur-Luen Tu
IPC: H01L27/146
Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes an image sensing element arranged within a substrate. One or more isolation structures are arranged within one or more trenches disposed on opposing sides of the image sensing element. The one or more isolation structures extend from a first surface of the substrate to within the substrate. The one or more isolation structures respectively include a reflective element configured to reflect electromagnetic radiation.
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公开(公告)号:US10319768B2
公开(公告)日:2019-06-11
申请号:US15688077
申请日:2017-08-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Chan Li , Cheng-Hsien Chou , Cheng-Yuan Tsai , Keng-Yu Chou , Yeur-Luen Tu
IPC: H01L27/146
Abstract: The present disclosure relates to an image sensor integrated chip having a deep trench isolation (DTI) structure having a reflective element. In some embodiments, the image sensor integrated chip includes an image sensing element arranged within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element and one or more absorption enhancement layers are arranged over and between the plurality of protrusions. A plurality of DTI structures are arranged within trenches disposed on opposing sides of the image sensing element and extend from the first side of the substrate to within the substrate. The plurality of DTI structures respectively include a reflective element having one or more reflective regions configured to reflect electromagnetic radiation. By reflecting electromagnetic radiation using the reflective elements, cross-talk between adjacent pixel regions is reduced, thereby improving performance of the image sensor integrated chip.
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公开(公告)号:US20180122844A1
公开(公告)日:2018-05-03
申请号:US15337328
申请日:2016-10-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Chan Li , Cheng-Hsien Chou , Sheng-Chau Chen , Cheng-Yuan Tsai , Chih-Hui Huang
IPC: H01L27/146
CPC classification number: H01L27/1464 , H01L27/14625 , H01L27/1463 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L27/14689
Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.
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