公开(公告)号：US20230207665A1

公开(公告)日：2023-06-29

申请号：US18178660

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chia-Cheng Tai ,  Tzu-Chan Weng ,  Yi-Wei Chiu ,  Chih Hsuan Cheng

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/823431 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/42316 ,  H01L29/66795

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

公开(公告)号：US20150228472A1

公开(公告)日：2015-08-13

申请号：US14177939

申请日：2014-02-11

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Yi-Wei Chiu ,  Hsin-Yi Tsai ,  Tzu-Chan Weng ,  Li-Te Hsu

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/823814 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract translation: 半导体器件包括硅基衬底，栅极结构和层叠的牺牲氧化物层。 栅极结构在硅基衬底上。 层叠的牺牲氧化物层具有硅基衬底上的第一部分和与栅极结构共形的第二部分，其中第一部分的第一厚度基本上与第二部分的第二厚度相同。 层叠的牺牲氧化物层包括自然氧化物层和氮氧化硅层。 天然氧化物层位于硅基衬底上，并与栅极结构保持一致。 氮氧化硅层与天然氧化物层共形。

公开(公告)号：US12074032B2

公开(公告)日：2024-08-27

申请号：US17340766

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Je Chuang ,  Wan-Chun Kuan ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L21/311 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01J37/32009 ,  H01J37/3244 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/67126 ,  H01L21/6719 ,  H01L21/67201 ,  H01J2237/334 ,  H01L21/823431 ,  H01L29/66742 ,  H01L29/66795

Abstract: A chamber door, such as an etch chamber door may be heated during etch processing to, e.g., prevent etching by-products from adhering to the etch chamber door. Such heating of the etch chamber door, however, can impact the processing parameters and result in non-uniform processing, such as non-uniform etching characteristics across a semiconductor wafer, for instance. An insulator, such as an insulating film covering surfaces of the heated door, can reduce or eliminate transmission of heat from the door to a work piece such as a semiconductor wafer and this reduce or eliminate the non-uniformity of the process results.

公开(公告)号：US11430893B2

公开(公告)日：2022-08-30

申请号：US16926521

申请日：2020-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yan-Ting Shen ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yu-Li Lin ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US20210407812A1

公开(公告)日：2021-12-30

申请号：US16916465

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01J37/32 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20210296135A1

公开(公告)日：2021-09-23

申请号：US17340766

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Je Chuang ,  Wan-Chun Kuan ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  H01L21/3065

Abstract: A chamber door, such as an etch chamber door may be heated during etch processing to, e.g., prevent etching by-products from adhering to the etch chamber door. Such heating of the etch chamber door, however, can impact the processing parameters and result in non-uniform processing, such as non-uniform etching characteristics across a semiconductor wafer, for instance. An insulator, such as an insulating film covering surfaces of the heated door, can reduce or eliminate transmission of heat from the door to a work piece such as a semiconductor wafer and this reduce or eliminate the non-uniformity of the process results.

公开(公告)号：US12125707B2

公开(公告)日：2024-10-22

申请号：US17814607

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/3065 ,  H01J37/32174 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20220367386A1

公开(公告)日：2022-11-17

申请号：US17815758

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Kuan ,  Chih-Teng Liao ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L23/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/306 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

公开(公告)号：US20210118816A1

公开(公告)日：2021-04-22

申请号：US17112029

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Kuan ,  Chih-Teng Liao ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L23/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/306 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

公开(公告)号：US10269938B2

公开(公告)日：2019-04-23

申请号：US15211409

申请日：2016-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Chin Hsu ,  Yi-Wei Chiu ,  Wen-Zhong Ho ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/322 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/762

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin structure over the base. The fin structure has sidewalls. The semiconductor device structure includes a passivation layer over the sidewalls. The passivation layer includes dopants. The dopants include at least one element selected from group 4A elements, and the dopants and the substrate are made of different materials. The semiconductor device structure includes an isolation layer over the base and surrounding the fin structure and the passivation layer. A first upper portion of the fin structure and a second upper portion of the passivation layer protrude from the isolation layer. The semiconductor device structure includes a gate electrode over the first upper portion of the fin structure and the second upper portion of the passivation layer.