公开(公告)号：US08946895B2

公开(公告)日：2015-02-03

申请号：US12389479

申请日：2009-02-20

申请人： Takahiko Kato ,  Hiroshi Nakano ,  Haruo Akahoshi ,  Yuuji Takada ,  Yoshimi Sudo ,  Tetsuo Fujiwara ,  Itaru Kanno ,  Tomoryo Shono ,  Yukinori Hirose

发明人： Takahiko Kato ,  Hiroshi Nakano ,  Haruo Akahoshi ,  Yuuji Takada ,  Yoshimi Sudo ,  Tetsuo Fujiwara ,  Itaru Kanno ,  Tomoryo Shono ,  Yukinori Hirose

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L22/12 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

摘要翻译： 具有包括可以减小表面空隙的碱性晶体结构的Cu布线的半导体器件和用于半导体器件的检查技术。 在半导体装置中，通过指定阻挡层和种子层，并设定具有一致位点网格（CSL）边界的占有比例（频率），表面空隙可以降低到当前实用水平的1/10以下，具有 对于Cu布线的所有晶界，晶界Sigma值为27以下，为60％以上。 或者，可以通过指定阻挡层和种子层并且将具有晶界Sigma值3的重合位点晶格（CSL）边界的占有比例（频率）设置为全部晶粒，可以获得类似的表面空隙降低效果 Cu布线的边界为40％以上。

公开(公告)号：US20110298097A1

公开(公告)日：2011-12-08

申请号：US13156021

申请日：2011-06-08

申请人： Manabu Sueyoshi ,  Seiji Muranaka ,  Tomoryo Shono ,  Itaru Kanno

发明人： Manabu Sueyoshi ,  Seiji Muranaka ,  Tomoryo Shono ,  Itaru Kanno

IPC分类号： H01L29/41 ,  H01L21/283

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is provided wherein stacked semiconductor substrates are electrically coupled together in a satisfactory state by a conductor buried in the interior of a through hole. A first semiconductor substrate includes a substrate having main surfaces, further includes a semiconductor element formed within and over the substrate, a wiring coupled to the semiconductor element electrically, and a conductive layer formed in the interior of a through hole, the through hole extending through mutually confronting first and second main surfaces as the main surfaces of the substrate and reaching the wiring. The first semiconductor substrate and a second semiconductor substrate are stacked and the conductive layer is coupled to a wiring of the second semiconductor substrate electrically. In a second main surface of the conductive layer, a recess is formed around an end portion of the through hole so that a bottom wall surface of the recess is present in the interior of the substrate. A conductive material which constitutes the conductive layer is filled in the interior of the recess.

摘要翻译： 提供一种半导体器件，其中堆叠的半导体衬底通过埋在通孔内部的导体在令人满意的状态下电耦合在一起。 第一半导体衬底包括具有主表面的衬底，还包括形成在衬底内和上面的半导体元件，电连接到半导体元件的布线，以及形成在通孔内部的导电层，所述通孔延伸穿过 相互面对的第一和第二主表面作为基板的主表面并到达布线。 层叠第一半导体衬底和第二半导体衬底，并且导电层电连接到第二半导体衬底的布线。 在导电层的第二主表面中，在通孔的端部周围形成凹部，使得凹部的底壁表面存在于基板的内部。 构成导电层的导电材料填充在凹部的内部。