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    Self-repairing redundancy for memory blocks in programmable logic devices
    1.
    发明授权
    Self-repairing redundancy for memory blocks in programmable logic devices 有权
    可编程逻辑器件中的存储器块的自修复冗余

    公开(公告)号：US07216277B1

    公开(公告)日：2007-05-08

    申请号：US10717040

    申请日：2003-11-18

    申请人： Tony K. Ngai ,  Jennifer Wong ,  Wayson J. Lowe

    发明人： Tony K. Ngai ,  Jennifer Wong ,  Wayson J. Lowe

    IPC分类号： G01R31/28 ,  G11C29/00

    CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/846

    摘要： Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

    摘要翻译： 可编程逻辑器件（PLD），包括自修复RAM电路，以及自动替换RAM阵列中有缺陷的列的方法。 包括冗余列的RAM电路在PLD配置顺序期间使用内置的自检（BIST）过程进行测试。 如果检测到有缺陷的列，则错误标志被存储在相关联的易失性存储器电路中。 BIST程序完成后，PLD配置过程继续。 错误标志的存在导致配置数据绕过故障列，并直接传递到替换列。 配置过程继续，直到电路的其余部分被配置，包括冗余列。 在其他实施例中，独立于PLD配置过程启动BIST过程。 当检测到有缺陷的列时，以对用户透明的方式，将数据从有缺陷的列分流到冗余列的用户操作恢复。

    Method and system for configuring an integrated circuit
    5.
    发明授权
    Method and system for configuring an integrated circuit 有权
    用于配置集成电路的方法和系统

    公开(公告)号：US07314174B1

    公开(公告)日：2008-01-01

    申请号：US10970964

    申请日：2004-10-22

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

    IPC分类号： G06K7/10 ,  G06K9/36 ,  G06K9/80

    CPC分类号： H03K19/177

    摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

    摘要翻译： 一种用于在集成电路中编程配置存储单元的系统。 该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

    Method of time multiplexing a programmable logic device
    10.
    发明授权
    Method of time multiplexing a programmable logic device 有权
    时间复用可编程逻辑器件的方法

    公开(公告)号：US06480954B2

    公开(公告)日：2002-11-12

    申请号：US09876745

    申请日：2001-06-06

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F900

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。