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    Method of forming layout of semiconductor device
    2.
    发明授权
    Method of forming layout of semiconductor device 有权

    公开(公告)号：US10707213B2

    公开(公告)日：2020-07-07

    申请号：US16178521

    申请日：2018-11-01

    申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    发明人： Chia-Hung Wang ,  En-Chiuan Liou ,  Chien-Hao Chen ,  Sho-Shen Lee ,  Yi-Ting Chen ,  Jhao-Hao Lee

    IPC分类号： H01L21/311 ,  H01L27/108 ,  H01L21/027 ,  H01L21/033

    摘要： A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20170025540A1

    公开(公告)日：2017-01-26

    申请号：US14841628

    申请日：2015-08-31

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： En-Chiuan Liou ,  Tang-Chun Weng ,  Chien-Hao Chen

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

    CPC分类号： H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

    摘要翻译： 半导体器件及其制造方法，半导体器件包括多个鳍状结构，沟槽，间隔层和虚拟栅极结构。 鳍状结构设置在基板上。 沟槽设置在翅片形结构之间。 间隔层设置在沟槽的侧壁上，其中间隔层具有比翅片形结构的顶表面低的顶表面。 虚拟栅极结构设置在鳍状结构上并横跨沟槽。

    MULTI-GATE FIELD-EFFECT TRANSISTOR PROCESS
    5.
    发明申请
    MULTI-GATE FIELD-EFFECT TRANSISTOR PROCESS 有权
    多栅极场效应晶体管工艺

    公开(公告)号：US20140295634A1

    公开(公告)日：2014-10-02

    申请号：US14306250

    申请日：2014-06-17

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

    摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

    摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从内向外减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

    OVERLAY MARK AND MEASUREMENT METHOD THEREOF
    6.
    发明申请
    OVERLAY MARK AND MEASUREMENT METHOD THEREOF 有权
    覆盖标记及其测量方法

    公开(公告)号：US20140132283A1

    公开(公告)日：2014-05-15

    申请号：US13674704

    申请日：2012-11-12

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kuo-Chun Huang ,  Chien-Hao Chen ,  Wen-Liang Huang

    IPC分类号： G01R27/26 ,  G01R27/02

    CPC分类号： G01R27/2605 ,  G01R27/02 ,  G03F1/38 ,  G03F1/42 ,  G03F7/70616 ,  G03F7/70633 ,  G06T2207/30148

    摘要： An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.

    摘要翻译： 提供了包括至少一个第一重叠标记和至少一个第二重叠标记的重叠标记。 第一覆盖标记包括多个第一条和交替布置的多个第一空间，并且第一空间不是恒定的。 第二覆盖标记包括多个第二条和交替排列的多个第二空间，第二空间是恒定的。 此外，第二覆盖标记部分地与第一覆盖标记重叠。

    PATTERNING METHOD AND OVERLAY MESUREMENT METHOD
    7.
    发明申请
    PATTERNING METHOD AND OVERLAY MESUREMENT METHOD 有权

    公开(公告)号：US20220392768A1

    公开(公告)日：2022-12-08

    申请号：US17341183

    申请日：2021-06-07

    申请人： United Microelectronics Corp.

    发明人： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

    IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L23/544 ,  H01L21/66 ,  G03F7/20

    摘要： The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

    METHOD OF FORMING LAYOUT OF SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF FORMING LAYOUT OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200111791A1

    公开(公告)日：2020-04-09

    申请号：US16178521

    申请日：2018-11-01

    申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    发明人： Chia-Hung Wang ,  En-Chiuan Liou ,  Chien-Hao Chen ,  Sho-Shen Lee ,  Yi-Ting Chen ,  Jhao-Hao Lee

    IPC分类号： H01L27/108 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

    摘要： A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.