公开(公告)号：US12237395B2

公开(公告)日：2025-02-25

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/768 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US20240349493A1

公开(公告)日：2024-10-17

申请号：US18754195

申请日：2024-06-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76895 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US10651040B2

公开(公告)日：2020-05-12

申请号：US15986797

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US20190319031A1

公开(公告)日：2019-10-17

申请号：US15972216

申请日：2018-05-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chun-Chieh Chiu ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Chih-Chien Liu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/28 ,  H01L21/22

Abstract: The present invention provides a bit line gate structure comprising a substrate, an amorphous silicon layer disposed on the substrate, a first doped region located in the amorphous silicon layer, a titanium silicon nitride (TiSiN) layer, located in the amorphous silicon layer, and a second doped region located in the TiSiN layer, the first doped region contacts the second doped region directly.

公开(公告)号：US20190252390A1

公开(公告)日：2019-08-15

申请号：US15900800

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Chun-Chieh Chiu

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/3215 ,  H01L21/285

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

公开(公告)号：US09755047B2

公开(公告)日：2017-09-05

申请号：US14924532

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US11799012B2

公开(公告)日：2023-10-24

申请号：US17012088

申请日：2020-09-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H10B12/00 ,  H01L21/285

CPC classification number: H01L29/4941 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/3213 ,  H01L29/42372 ,  H10B12/05 ,  H10B12/482 ,  H01L21/28518 ,  H01L21/28556 ,  H10B12/30

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20200258889A1

公开(公告)日：2020-08-13

申请号：US16858729

申请日：2020-04-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Chun-Chieh Chiu

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/3215 ,  H01L23/532

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

公开(公告)号：US20190319107A1

公开(公告)日：2019-10-17

申请号：US15985730

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20190057895A1

公开(公告)日：2019-02-21

申请号：US15711854

申请日：2017-09-21

Applicant: United Microelectronics Corp.

Inventor： Li-Han Chen ,  Chun-Chieh Chiu ,  Wei-Chuan Tsai ,  Yen-Tsai Yi

IPC: H01L21/74 ,  H01L21/768

Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.