公开(公告)号：US20250098273A1

公开(公告)日：2025-03-20

申请号：US18969201

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

公开(公告)号：US20250098271A1

公开(公告)日：2025-03-20

申请号：US18969172

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US12147155B2

公开(公告)日：2024-11-19

申请号：US17359687

申请日：2021-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Cheng Yang ,  Chung-Yi Chiu

IPC: G03F1/36 ,  G03F7/00 ,  G06F30/27 ,  G06N5/04 ,  G06N20/00 ,  G06F119/18 ,  G06F119/22

Abstract: A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

公开(公告)号：US11927887B2

公开(公告)日：2024-03-12

申请号：US17348806

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guo-Xin Hu ,  Yuh-Kwei Chao ,  Chung-Yi Chiu

IPC: G03F7/00 ,  G06F18/214 ,  G06N20/00 ,  G06T7/00 ,  G06V10/44

CPC classification number: G03F7/70441 ,  G06F18/214 ,  G06N20/00 ,  G06T7/0004 ,  G06V10/44 ,  G06T2207/20081 ,  G06T2207/30148

Abstract: An optical proximity correction (OPC) operation method and an OPC operation device are provided. The OPC operation method includes the following steps. A mask layout is obtained. If the mask layout contains at least one defect hotspot, at least one partial area pattern is extracted from the mask layout according to the at least defect hotspot. A machine learning model is used to analyze the local area pattern to obtain at least one OPC strategy. The OPC strategy is implemented to correct the mask layout.

公开(公告)号：US20230378313A1

公开(公告)日：2023-11-23

申请号：US17838258

申请日：2022-06-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/42316 ,  H01L29/778

Abstract: A manufacturing method of a semiconductor device includes the following steps. A gate structure is formed on a III-V compound semiconductor layer. A gate silicide layer and a source/drain silicide layer are formed by an anneal process. The gate silicide layer is formed on the gate structure, the source/drain silicide layer is formed on the III-V compound semiconductor layer, and a material composition of the gate silicide layer is different from a material composition of the source/drain silicide layer.

公开(公告)号：US20230136441A1

公开(公告)日：2023-05-04

申请号：US17541226

申请日：2021-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Yu Lin ,  Po-Kai Hsu ,  Chung-Yi Chiu

IPC: H01L27/24 ,  H01L45/00

Abstract: A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.

公开(公告)号：US20170194193A1

公开(公告)日：2017-07-06

申请号：US15465606

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L21/762 ,  H01L29/161 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

公开(公告)号：US20250072075A1

公开(公告)日：2025-02-27

申请号：US18946839

申请日：2024-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film

公开(公告)号：US20240420991A1

公开(公告)日：2024-12-19

申请号：US18219107

申请日：2023-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jing-Wen Huang ,  Chih-Yuan Wen ,  Lung-En Kuo ,  Po-Chang Lin ,  Kun-Yuan Liao ,  Chung-Yi Chiu

IPC: H01L21/762 ,  H01L27/088

Abstract: A semiconductor device with a deep trench isolation and a shallow trench isolation includes a substrate. The substrate is divided into a high voltage transistor region and a low voltage transistor region. A deep trench is disposed within the high voltage transistor region. The deep trench includes a first trench and a second trench. The first trench includes a first bottom. The second trench extends from the first bottom toward a bottom of the substrate. A first shallow trench and a second shallow trench are disposed within the low voltage transistor region. A length of the first shallow trench is the same as a length of the second trench. An insulating layer fills in the first trench, the second trench, the first shallow trench and the second shallow trench.

公开(公告)号：US20240128324A1

公开(公告)日：2024-04-18

申请号：US17990763

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Chung-Yi Chiu

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1606 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/66045 ,  H01L29/78

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.