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    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    1.
    发明公开
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20240130141A1

    公开(公告)日：2024-04-18

    申请号：US18395649

    申请日：2023-12-25

    Applicant: United Microelectronics Corp.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  H01L23/528 ,  H10N50/80

    CPC classification number: H10B61/22 ,  H01L23/528 ,  H10N50/80 ,  G11C11/161

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

    Layout pattern for magnetoresistive random access memory
    3.
    发明授权
    Layout pattern for magnetoresistive random access memory 有权

    公开(公告)号：US11374055B2

    公开(公告)日：2022-06-28

    申请号：US16792271

    申请日：2020-02-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H01L27/22 ,  H01L23/528 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.

    Semiconductor structure and method for forming the same
    5.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US10937946B2

    公开(公告)日：2021-03-02

    申请号：US16541172

    申请日：2019-08-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

    IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

    MAGNETIC MEMORY CELL
    6.
    发明申请
    MAGNETIC MEMORY CELL 有权

    公开(公告)号：US20210020694A1

    公开(公告)日：2021-01-21

    申请号：US16812354

    申请日：2020-03-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  Hung-Yueh Chen ,  Ya-Huei Tsai ,  Yu-Ping Wang

    IPC: H01L27/22 ,  H01L23/532 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H01L43/02

    Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

    FIN STRUCTURE CUTTING PROCESS
    10.
    发明申请
    FIN STRUCTURE CUTTING PROCESS 有权
    FIN结构切割工艺

    公开(公告)号：US20170047244A1

    公开(公告)日：2017-02-16

    申请号：US15336811

    申请日：2016-10-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

    IPC: H01L21/762 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/02

    CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

    Abstract translation: 翅片结构切割过程包括以下步骤。 在基板中形成有四个翅片结构，其中包括第一翅片结构，第二翅片结构，第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分，从而由第二鳍结构形成第一凸起，以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构，但是将第一凸起保持在第一鳍结构旁边。 此外，本发明提供了一种通过所述方法形成的翅片结构。

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