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    Electronic component with improved precharging
    3.
    发明申请
    Electronic component with improved precharging 审中-公开
    电子元件具有改进的预充电

    公开(公告)号：US20060250868A1

    公开(公告)日：2006-11-09

    申请号：US11402194

    申请日：2006-04-11

    申请人： Florian Schnabel ,  Helmut Schneider

    发明人： Florian Schnabel ,  Helmut Schneider

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2207/2227

    摘要： An electronic component has a first bit line and a second bit line, which are coupled to a plurality of memory cells, a line for providing a precharging potential, a resistance component which is connected to the line, a first switch which is coupled between the resistance component and the first bit line for connection of the first bit line to the resistance component, and a second switch, which is coupled between the resistance component and the second bit line, for connection of the second bit line to the resistance component. The electrical resistance of the resistance component is controllable in order to assume a predetermined first resistance value or a predetermined second resistance value which is higher than the first resistance value.

    摘要翻译： 电子部件具有第一位线和第二位线，其耦合到多个存储器单元，用于提供预充电电位的线，连接到线的电阻分量，第一开关，其耦合在 电阻分量和用于将第一位线连接到电阻分量的第一位线，以及耦合在电阻分量和第二位线之间的用于将第二位线连接到电阻分量的第二开关。 电阻分量的电阻是可控制的，以便呈现比第一电阻值高的预定第一电阻值或预定第二电阻值。

    Memory component having a novel arrangement of the bit lines
    5.
    发明申请
    Memory component having a novel arrangement of the bit lines 失效
    存储器组件具有位线的新颖布置

    公开(公告)号：US20060152988A1

    公开(公告)日：2006-07-13

    申请号：US11301354

    申请日：2005-12-12

    申请人： Florian Schnabel ,  Helmut Schneider

    发明人： Florian Schnabel ,  Helmut Schneider

    IPC分类号： G11C7/00

    CPC分类号： G11C5/025 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10897

    摘要： A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

    摘要翻译： 存储器组件包括布置有存储器单元的多个位线和排列成行的多个读出放大器，每个读出放大器连接到两个位线。 连接到行中的第一读出放大器的位线被布置成与连接到同一行中的第二读出放大器的位线相邻。

    Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory
    6.
    发明申请
    Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory 审中-公开
    用于向半导体存储器中的存储单元进行写入和/或读取的装置和方法

    公开(公告)号：US20060133172A1

    公开(公告)日：2006-06-22

    申请号：US11283493

    申请日：2005-11-18

    申请人： Florian Schnabel ,  Jens Polney

    发明人： Florian Schnabel ,  Jens Polney

    IPC分类号： G11C7/04

    CPC分类号： G11C7/04 ,  G11C5/146 ,  G11C11/4074 ,  G11C11/409

    摘要： The invention proposes an apparatus for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the apparatus has a device which is used to influence a threshold voltage for the selection transistor contrary to the influence of an ambient temperature. The invention also proposes a method for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the method comprises the following method steps: a) an ambient temperature for the memory cell is ascertained, and b) an electrical voltage is applied to a substrate well in the selection transistor as a function of the ascertained ambient temperature such that a threshold voltage for the selection transistor is influenced contrary to the influence of an ambient temperature.

    摘要翻译： 本发明提出了一种用于在具有选择晶体管和存储电容器的半导体存储器中从存储单元写入和/或读取的装置，其中该装置具有用于影响与该选择晶体管相反的选择晶体管的阈值电压的装置 环境温度的影响。 本发明还提出了一种用于在具有选择晶体管和存储电容器的半导体存储器中的存储单元的写入和/或读取方法，其中该方法包括以下方法步骤：a）确定存储单元的环境温度 并且b）作为所确定的环境温度的函数，在选择晶体管中的基板上施加电压，使得选择晶体管的阈值电压与环境温度的影响相反。

    Memory component having a novel arrangement of the bit lines
    9.
    发明授权
    Memory component having a novel arrangement of the bit lines 失效
    存储器组件具有位线的新颖布置

    公开(公告)号：US07414906B2

    公开(公告)日：2008-08-19

    申请号：US11301354

    申请日：2005-12-12

    申请人： Florian Schnabel ,  Helmut Schneider

    发明人： Florian Schnabel ,  Helmut Schneider

    IPC分类号： G11C7/00

    CPC分类号： G11C5/025 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10885 ,  H01L27/10897

    摘要： A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

    摘要翻译： 存储器组件包括布置有存储器单元的多个位线和排列成行的多个读出放大器，每个读出放大器连接到两个位线。 连接到行中的第一读出放大器的位线被布置成与连接到同一行中的第二读出放大器的位线相邻。