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19 条记录 (耗时 0.04 秒)

    Memory cell, memory cell configuration and fabrication method
    4.
    发明授权
    Memory cell, memory cell configuration and fabrication method 有权
    存储单元，存储单元配置和制造方法

    公开(公告)号：US06844584B2

    公开(公告)日：2005-01-18

    申请号：US09927573

    申请日：2001-08-09

    申请人： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

    发明人： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

    IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    摘要： Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

    摘要翻译： 每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。 栅电极通过介电材料与半导体材料分离。 至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氧化物 - 氧化物层序列。 层序列是为了在源极和漏极处俘获电荷载体而提供的。

    Semiconductor memory having charge trapping memory cells and fabrication method
    6.
    发明授权
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US07184291B2

    公开(公告)日：2007-02-27

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： G11C5/06

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Data carrier card
    7.
    发明申请
    Data carrier card 有权
    数据载体卡

    公开(公告)号：US20050045730A1

    公开(公告)日：2005-03-03

    申请号：US10925882

    申请日：2004-08-23

    申请人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

    发明人： Jurgen Fischer ,  Herbert Palm ,  Frank Puschner ,  Josef Willer

    IPC分类号： G06K19/077 ,  G06K19/06

    CPC分类号： G06K19/07747 ,  G06K19/07743 ,  H01L2224/48091 ,  H01L2924/00014

    摘要： Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.

    摘要翻译： 数据载体卡具有扁平形式的卡体，并且具有凹槽，载体，布置在载体上并插入卡体凹部中的芯片，外部接触元件布置在载体上并电连接到芯片通孔导体 并且覆盖与载体可操作地连接的凹部的盖，使得载体沿着凹部中的底部保持，其中外部接触元件和芯片布置在载体的同一侧上。

    Method for fabricating a memory cell
    8.
    发明授权
    Method for fabricating a memory cell 有权
    用于制造存储单元的方法

    公开(公告)号：US06794249B2

    公开(公告)日：2004-09-21

    申请号：US10378101

    申请日：2003-02-28

    申请人： Herbert Palm ,  Josef Willer

    发明人： Herbert Palm ,  Josef Willer

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L29/66833

    摘要： An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.

    摘要翻译： 导电层或层序列优选地包括施加到金属硅化物或多晶硅层的含金属层以降低掩埋位线的电阻。 层或层序列已经以带状形式图案化，以对应于位线，并且布置在具有ONO存储层序列的存储晶体管的源极/漏极区域和布置在沟槽中的栅极电极。 金属硅化物优选为硅化钴，并且含金属层优选为硅化钨或WN / W。

    Semiconductor memory having charge trapping memory cells and fabrication method
    9.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US20050286296A1

    公开(公告)日：2005-12-29

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Time recording device and a time recording method employing a semiconductor element
    10.
    发明授权
    Time recording device and a time recording method employing a semiconductor element 有权
    时间记录装置和采用半导体元件的时间记录方法

    公开(公告)号：US06909294B2

    公开(公告)日：2005-06-21

    申请号：US10638598

    申请日：2003-08-11

    申请人： Herbert Palm ,  Hans Taddiken ,  Erdmute Wohlrab

    发明人： Herbert Palm ,  Hans Taddiken ,  Erdmute Wohlrab

    IPC分类号： G04F10/10 ,  G04F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G01R31/26 ,  H01L23/58

    CPC分类号： H01L29/511 ,  G04F1/005 ,  G04F10/10 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/792

    摘要： A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

    摘要翻译： 时间记录装置采用浮动栅极单元，其中在浮动栅极和控制栅极之间提供ON层结构或ONO层结构。 提供电荷注入单元，通过向控制栅电极施加电压或电压脉冲，注入到电荷注入单元中的电荷浓度的中心，将电荷注入到浮置栅电极中并进入ON结构或ONO结构的氮化物层 氮化物层位于层序列的氧化物层和氮化物层之间的界面处。 时间记录装置还包括用于记录从电荷注入以来经过的时间的单元，其基于由氮化物层中的电荷的浓度中心偏移导致的沟道区的透射行为的变化 接口。