公开(公告)号：US06870263B1

公开(公告)日：2005-03-22

申请号：US09052688

申请日：1998-03-31

申请人： Lawrence A. Clevenger ,  Ronald G. Filippi ,  Mark Hoinkis ,  Jeffery L. Hurd ,  Roy C. Iggulden ,  Herbert Palm ,  Hans W. Poetzlberger ,  Kenneth P. Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim A. Mehter

发明人： Lawrence A. Clevenger ,  Ronald G. Filippi ,  Mark Hoinkis ,  Jeffery L. Hurd ,  Roy C. Iggulden ,  Herbert Palm ,  Hans W. Poetzlberger ,  Kenneth P. Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim A. Mehter

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

摘要翻译： 用于互连具有改进的可靠性的集成电路部件的导体。 导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。 已经发现，低纹理导体导致改善的电迁移寿命。

公开(公告)号：US20050116342A1

公开(公告)日：2005-06-02

申请号：US11024067

申请日：2004-12-28

申请人： Lawrence Clevenger ,  Ronald Filippi ,  Mark Hoinkis ,  Jeffery Hurd ,  Roy Iggulden ,  Herbert Palm ,  Hans Poetzlberger ,  Kenneth Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim Mehter

发明人： Lawrence Clevenger ,  Ronald Filippi ,  Mark Hoinkis ,  Jeffery Hurd ,  Roy Iggulden ,  Herbert Palm ,  Hans Poetzlberger ,  Kenneth Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim Mehter

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

公开(公告)号：US06221757B1

公开(公告)日：2001-04-24

申请号：US09234341

申请日：1999-01-20

申请人： Sven Schmidbauer ,  Alexander Ruf ,  Florian Schnabel ,  Mark Hoinkis ,  Stefan Weber

发明人： Sven Schmidbauer ,  Alexander Ruf ,  Florian Schnabel ,  Mark Hoinkis ,  Stefan Weber

IPC分类号： H01L214763

CPC分类号： H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic structure is formed on a first layer or a substrate. The first layer or substrate is formed with grooves and contact openings. A metal nitride layer of TiN or WN covers the first layer or the substrate at least partially. An alpha-phase tantalum layer is deposited on top of the metal nitride layer. Finally, a metal is deposited to completely fill the grooves and the contact openings.

摘要翻译： 在第一层或衬底上形成微电子结构。 第一层或衬底形成有凹槽和接触开口。 TiN或WN的金属氮化物层至少部分地覆盖第一层或衬底。 将α相钽层沉积在金属氮化物层的顶部。 最后，沉积金属以完全填充凹槽和接触开口。

公开(公告)号：US6057236A

公开(公告)日：2000-05-02

申请号：US105644

申请日：1998-06-26

申请人： Larry Clevenger ,  Mark Hoinkis ,  Roy C. Iggulden ,  Stefan J. Weber

发明人： Larry Clevenger ,  Mark Hoinkis ,  Roy C. Iggulden ,  Stefan J. Weber

IPC分类号： H01L21/3205 ,  C23C14/14 ,  C23C14/58 ,  C23C16/56 ,  C23C28/02 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76868 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002

摘要： Improved methods for forming metal-filled structures in openings on substrates for integrated circuit devices are obtained by the formation of a discontinuous metal liner by CVD in an opening to be filled. The discontinuous metal liner surprisingly provides wetting equivalent to or better than continuous layer CVD liners. The CVD step is followed by depositing a further amount of metal by physical vapor deposition over the discontinuous layer in the opening, and reflowing the further amount of metal to obtain the metal-filled structure.The interior surface of the opening is preferably a conductive material such as titanium nitride. Preferably, the discontinuous metal layer is made of aluminum. The metal deposited by PVD is preferably aluminum or an aluminum alloy. The methods of the invention are especially useful for the filling of contact holes, damascene trenches and dual damascene trenches. The methods of the invention are especially useful for filling structures having an opening width less than 250 nm.

摘要翻译： 通过在待填充的开口中通过CVD形成不连续的金属衬垫来获得用于在集成电路器件的衬底上的开口中形成金属填充结构的改进方法。 不连续的金属衬垫令人惊讶地提供了与连续层CVD衬垫相当或更好的润湿。 CVD步骤之后，通过在开口中的不连续层上的物理气相沉积沉积更多量的金属，再回流另外的金属以获得填充金属的结构。 开口的内表面优选为诸如氮化钛的导电材料。 优选地，不连续金属层由铝制成。 通过PVD沉积的金属优选为铝或铝合金。 本发明的方法对于填充接触孔，镶嵌沟槽和双镶嵌沟槽特别有用。 本发明的方法对于填充具有小于250nm的开口宽度的结构特别有用。

公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US07494915B2

公开(公告)日：2009-02-24

申请号：US11463447

申请日：2006-08-09

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US07122462B2

公开(公告)日：2006-10-17

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

公开(公告)号：US07368804B2

公开(公告)日：2008-05-06

申请号：US10439874

申请日：2003-05-16

申请人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

发明人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

IPC分类号： H01L23/58 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： C23F1/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US20050221610A1

公开(公告)日：2005-10-06

申请号：US11144980

申请日：2005-06-03

申请人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis Warner ,  Erdem Kaltalioglu

发明人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis Warner ,  Erdem Kaltalioglu

IPC分类号： H01L23/522 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。