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14 条记录 (耗时 0.043 秒)

    Method of forming a solute-enriched layer in a substrate surface and article formed thereby
    2.
    发明授权
    Method of forming a solute-enriched layer in a substrate surface and article formed thereby 有权
    在基材表面形成富含溶质层的方法和由此形成的制品

    公开(公告)号：US06413866B1

    公开(公告)日：2002-07-02

    申请号：US09525367

    申请日：2000-03-15

    申请人： Horatio S. Wildman ,  Lawrence A. Clevenger ,  Chenting Lin ,  Kenneth P. Rodbell ,  Stefan Weber ,  Roy C. Iggulden ,  Maria Ronay ,  Florian Schnabel

    发明人： Horatio S. Wildman ,  Lawrence A. Clevenger ,  Chenting Lin ,  Kenneth P. Rodbell ,  Stefan Weber ,  Roy C. Iggulden ,  Maria Ronay ,  Florian Schnabel

    IPC分类号： H01L2144

    CPC分类号： H01L21/7685 ,  H01L21/321 ,  H01L21/76867 ,  H01L21/76888 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.

    摘要翻译： 一种使用最初溶解在基片材料中的溶质材料来富集基片的表面的方法，以使溶质材料在基片表面上均匀分散。 该方法通常需要使用比溶质材料对选择的反应剂更具反应性的溶剂材料。 使基板的表面与反应剂反应，以优先在基材的表面形成溶剂材料的反应化合物。 当化合物层发展时，溶质材料从化合物层中分离或扩散到下面的衬底中，使得最接近化合物层的衬底的区域变得富集溶质材料。 然后除去化合物层的至少一部分而不去除底物的下面的富集区域。 对于微电路应用，该方法可用于通过元素铜来丰富铝线的表面，以提高线路的电迁移能力。

    Process of enclosing via for improved reliability in dual damascene interconnects
    3.
    发明授权
    Process of enclosing via for improved reliability in dual damascene interconnects 有权
    封装通孔的过程可提高双镶嵌互连中的可靠性

    公开(公告)号：US06383920B1

    公开(公告)日：2002-05-07

    申请号：US09757894

    申请日：2001-01-10

    申请人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

    发明人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

    IPC分类号： H01L214763

    CPC分类号： H01L21/76847 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

    摘要翻译： 本发明一般涉及在双镶嵌工艺中封闭通孔的方法。 在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽 在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。 或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在 双镶嵌工艺。 阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。

    Gas dielectric structure forming methods
    5.
    发明授权
    Gas dielectric structure forming methods 失效
    气体介电结构成型方法

    公开(公告)号：US07560375B2

    公开(公告)日：2009-07-14

    申请号：US10711697

    申请日：2004-09-30

    申请人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang

    发明人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.

    摘要翻译： 通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。 特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。 本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

    Detection of residual liner materials after polishing in damascene process
    7.
    发明授权
    Detection of residual liner materials after polishing in damascene process 失效
    在镶嵌工艺中抛光后残留衬垫材料的检测

    公开(公告)号：US07361584B2

    公开(公告)日：2008-04-22

    申请号：US10904329

    申请日：2004-11-04

    申请人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

    发明人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

    摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。

    CVD/PVD method of filling structures using discontinuous CVD AL liner
    9.
    发明授权
    CVD/PVD method of filling structures using discontinuous CVD AL liner 失效
    使用不连续CVD AL衬垫填充结构的CVD / PVD方法

    公开(公告)号：US6057236A

    公开(公告)日：2000-05-02

    申请号：US105644

    申请日：1998-06-26

    申请人： Larry Clevenger ,  Mark Hoinkis ,  Roy C. Iggulden ,  Stefan J. Weber

    发明人： Larry Clevenger ,  Mark Hoinkis ,  Roy C. Iggulden ,  Stefan J. Weber

    IPC分类号： H01L21/3205 ,  C23C14/14 ,  C23C14/58 ,  C23C16/56 ,  C23C28/02 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/76868 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002

    摘要： Improved methods for forming metal-filled structures in openings on substrates for integrated circuit devices are obtained by the formation of a discontinuous metal liner by CVD in an opening to be filled. The discontinuous metal liner surprisingly provides wetting equivalent to or better than continuous layer CVD liners. The CVD step is followed by depositing a further amount of metal by physical vapor deposition over the discontinuous layer in the opening, and reflowing the further amount of metal to obtain the metal-filled structure.The interior surface of the opening is preferably a conductive material such as titanium nitride. Preferably, the discontinuous metal layer is made of aluminum. The metal deposited by PVD is preferably aluminum or an aluminum alloy. The methods of the invention are especially useful for the filling of contact holes, damascene trenches and dual damascene trenches. The methods of the invention are especially useful for filling structures having an opening width less than 250 nm.

    摘要翻译： 通过在待填充的开口中通过CVD形成不连续的金属衬垫来获得用于在集成电路器件的衬底上的开口中形成金属填充结构的改进方法。 不连续的金属衬垫令人惊讶地提供了与连续层CVD衬垫相当或更好的润湿。 CVD步骤之后，通过在开口中的不连续层上的物理气相沉积沉积更多量的金属，再回流另外的金属以获得填充金属的结构。 开口的内表面优选为诸如氮化钛的导电材料。 优选地，不连续金属层由铝制成。 通过PVD沉积的金属优选为铝或铝合金。 本发明的方法对于填充接触孔，镶嵌沟槽和双镶嵌沟槽特别有用。 本发明的方法对于填充具有小于250nm的开口宽度的结构特别有用。

    Semiconductor structure and method of fabrication including forming aluminum columns
    10.
    发明授权
    Semiconductor structure and method of fabrication including forming aluminum columns 有权
    半导体结构和制造方法，包括形成铝柱

    公开(公告)号：US06635564B1

    公开(公告)日：2003-10-21

    申请号：US09662424

    申请日：2000-09-14

    申请人： Stefan Weber ,  Roy C. Iggulden

    发明人： Stefan Weber ,  Roy C. Iggulden

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76876 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with a composite layer of titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A physical vapor deposited layer of aluminum is then formed while the structure is heated to about 400 degrees C. to completly fill the vias and to overfill same to form a blanket layer of aluminum above the first insulating layer (34). The blanket layer of aluminum is then patterned and portions not covered by the pattern are removed to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.

    摘要翻译： 在覆盖半导体衬底（主体）的第一绝缘层中形成的高纵横比通孔以两种方式填充有导体，这两者都减少了加工步骤的数量，并允许对准工具（步进器）对准定位和重叠标记。 每个通孔的侧壁和底部涂覆有钛，氮化钛和化学气相沉积的铝层的复合层。 然后在将结构加热至约400℃的同时形成铝的物理气相沉积层，以完全填充通孔并过度填充其，以在第一绝缘层（34）上方形成覆盖层的铝。 然后将铝的覆盖层图案化，并且去除不被图案覆盖的部分以产生铝列。 然后围绕铝列形成第二绝缘层。 在第二绝缘层的顶部的列的端部位于相对公平的平面中，步进器可以相对容易地对准图案。