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1.发明申请公开(公告)号：US20090167429A1
公开(公告)日：2009-07-02
申请号：US12013221
申请日：2008-01-11
IPC分类号： G01R31/28
CPC分类号： G01R31/2879 , G01R31/3161
摘要： One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.
摘要翻译： 一个实施例涉及片上功率放大器（PA）测试电路。 在一个实施例中，PA测试电路包括被配置为产生射频（RF）信号的可控振荡器（CO），调谐到射频的并联谐振电路，耦合到CO的预功率放大器（PPA）和 并联谐振电路，PPA被配置为放大并将RF信号从PPA的输出驱动到负载中。 测试电路还可以包括被配置为将来自CO的RF信号耦合到PPA的输入的第一传输门。 PA测试电路的一种测试方法包括用RF信号强迫PPA，测量PPA的特性，从特征测量确定应力退化，并重复应力和特征测量，直到达到最大应力退化或最大应力 已被应用。
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2.发明授权Methodology for assessing degradation due to radio frequency excitation of transistors 有权评估由于晶体管射频激发引起的退化的方法公开(公告)号：US07974595B2
公开(公告)日：2011-07-05
申请号：US12013221
申请日：2008-01-11
CPC分类号： G01R31/2879 , G01R31/3161
摘要： One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.
摘要翻译： 一个实施例涉及片上功率放大器（PA）测试电路。 在一个实施例中，PA测试电路包括被配置为产生射频（RF）信号的可控振荡器（CO），调谐到射频的并联谐振电路，耦合到CO的预功率放大器（PPA）和 并联谐振电路，PPA被配置为放大并将RF信号从PPA的输出驱动到负载中。 测试电路还可以包括被配置为将来自CO的RF信号耦合到PPA的输入的第一传输门。 PA测试电路的一种测试方法包括用RF信号强迫PPA，测量PPA的特性，从特征测量确定应力退化，并重复应力和特征测量，直到达到最大应力退化或最大应力 已被应用。
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公开(公告)号：US08472437B2
公开(公告)日：2013-06-25
申请号：US13026777
申请日：2011-02-14
申请人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
发明人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
CPC分类号： H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
摘要： Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
摘要翻译： 本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。 路由器或交换机在输入端口ASIC处接收数据包。 输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。 使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。
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公开(公告)号：US08471302B2
公开(公告)日：2013-06-25
申请号：US12911488
申请日：2010-10-25
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/088
摘要： Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes.
摘要翻译： 中和电容通常用于补偿米勒效应; 然而，在较高的频率下，引入到互连中的寄生电感可以影响中和。 这里，已经提供了一种布置，其中MOS电容器与互补晶体管合并。 通过具有这种合并器件，布局紧凑并且减小了互连面积，这降低了在较高频率（即，毫米波或太赫兹）处的寄生电感的影响。 该布局也可用于实现线性增强方案。
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5.发明申请CHIP TO DIELECTRIC WAVEGUIDE INTERFACE FOR SUB-MILLIMETER WAVE COMMUNICATIONS LINK 有权切割到用于亚微波通信的电介质波导接口公开(公告)号：US20120068891A1
公开(公告)日：2012-03-22
申请号：US12887323
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
IPC分类号： H01Q1/24
CPC分类号： H01Q3/44 , H01L23/3107 , H01L23/66 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2223/6677 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/3011 , H01Q3/26 , H01Q9/0407 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译： 在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。 然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。 该系统允许不对准，同时提供增加的通信带宽。
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公开(公告)号：US20120098069A1
公开(公告)日：2012-04-26
申请号：US12911488
申请日：2010-10-25
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/088
摘要： Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes.
摘要翻译： 中和电容通常用于补偿米勒效应; 然而，在较高的频率下，引入到互连中的寄生电感可以影响中和。 这里，已经提供了一种布置，其中MOS电容器与互补晶体管合并。 通过具有这种合并器件，布局紧凑并且减小了互连面积，这降低了在较高频率（即，毫米波或太赫兹）处的寄生电感的影响。 该布局也可用于实现线性增强方案。
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公开(公告)号：US20120086505A1
公开(公告)日：2012-04-12
申请号：US12899390
申请日：2010-10-06
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L25/00
CPC分类号： H03D7/1458 , H03D7/1433 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0019 , H03D2200/0082
摘要： Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.
摘要翻译： 传统上，混频器已经围绕输入信号对称布置，这导致了由于本机振荡器信号的自混合或馈通引起的问题。 然而，这里，混频器的布置已经改变，以便大体上避免本地振荡器信号的自混合。 特别地，切换核心中的晶体管根据所接收的本地振荡器信号的部分被合并。 这又导致承载本地振荡器信号的不同部分的导体被分离（或不具有任何交叉），以便通常消除本机振荡器信号的自混合或馈通。 使用这种安排实现的复杂IQ混音器可从改进的边带抑制和镜像抑制中获益。
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公开(公告)号：US20120242403A1
公开(公告)日：2012-09-27
申请号：US13490264
申请日：2012-06-06
申请人： Siraj Akhtar
发明人： Siraj Akhtar
IPC分类号： H01L25/00
CPC分类号： H03D7/1458 , H03D7/1433 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0019 , H03D2200/0082
摘要： Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.
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公开(公告)号：US07999615B2
公开(公告)日：2011-08-16
申请号：US13008489
申请日：2011-01-18
IPC分类号： H03F3/45
CPC分类号： H03F3/245 , H03F3/195 , H03F3/45179 , H03F2200/18 , H03F2200/336 , H03F2200/387 , H03F2200/451 , H03F2200/537 , H03F2200/541 , H03F2200/72 , H03F2203/45154 , H03F2203/45304 , H03F2203/45311 , H03G1/0029 , H03G7/001 , H04L27/362
摘要： A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first subtracting transistor. The second leg has a second input line, a second output line, a second ON transistor, a second control transistor and a second subtracting transistor. The second input line can provide a second input current. The second output line can provide a second output current. The first input line is arranged to provide a first input current to each of the first ON transistor, the first control transistor and the first subtracting transistor. The second input line is arranged to provide a second input current to each of the second ON transistor, the second control transistor and the second subtracting transistor. The first output line is in electrical connection with each of the first ON transistor, the first control transistor and the second subtracting transistor. The second output line is in electrical connection with each of the second ON transistor, the second control transistor and the first subtracting transistor.
摘要翻译： 电流消除CMOS可变增益放大器包括第一支路和第二支路。 第一支路具有第一输入线，第一输出线，第一ON晶体管，第一控制晶体管和第一减法晶体管。 第二支路具有第二输入线，第二输出线，第二ON晶体管，第二控制晶体管和第二减法晶体管。 第二输入线可以提供第二输入电流。 第二输出线可以提供第二输出电流。 第一输入线被布置成向第一ON晶体管，第一控制晶体管和第一减法晶体管中的每一个提供第一输入电流。 第二输入线被布置成向第二ON晶体管，第二控制晶体管和第二减法晶体管中的每一个提供第二输入电流。 第一输出线与第一ON晶体管，第一控制晶体管和第二减法晶体管中的每一个电连接。 第二输出线与第二ON晶体管，第二控制晶体管和第一减法晶体管中的每一个电连接。
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10.发明申请Local oscillator incorporating phase command exception handling utilizing a quadrature switch 有权采用正交开关的本地振荡器包含相位命令异常处理公开(公告)号：US20080002788A1
公开(公告)日：2008-01-03
申请号：US11852939
申请日：2007-09-10
申请人： Siraj Akhtar , Mehmet Ipek , Robert Staszewski
发明人： Siraj Akhtar , Mehmet Ipek , Robert Staszewski
CPC分类号： H04L27/361 , H03B19/14 , H03C5/00 , H04B1/0483
摘要： A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.
摘要翻译： 一种新颖有用的本地振荡器生成装置和采用异常处理机制的方法，其允许具有有限调制范围的振荡器来处理诸如3G WCDMA等现代宽带无线标准所要求的大调制范围。可控振荡器产生 RF信号根据输入命令信号具有四个正交相位。 异常处理程序将频率命令信息与阈值进行比较。 如果超过阈值，则产生相位跳变和残留频率指令。 剩余频率指令被输入到可产生具有四个正交相位的RF信号的振荡器。 相位跳变被输入到正交开关，其用于选择四个正交相位信号中的一个作为输出RF信号，然后馈送到数字功率放大器。
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