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    Semiconductor Memory Device and Method of Fabricating the Same
    1.
    发明申请
    Semiconductor Memory Device and Method of Fabricating the Same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20140220750A1

    公开(公告)日：2014-08-07

    申请号：US14171056

    申请日：2014-02-03

    申请人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    发明人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

    摘要翻译： 提供半导体器件及其制造方法。 该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案 数据存储层的侧壁将被电连接到基板。 电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。

    Semiconductor memory device and method of fabricating the same
    3.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09224753B2

    公开(公告)日：2015-12-29

    申请号：US14599933

    申请日：2015-01-19

    申请人： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

    发明人： Tai-Soo Lim ,  Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Myoungbum Lee ,  Yong Chae Jung

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/49

    CPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827

    摘要： Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

    摘要翻译： 提供半导体存储器件及其制造方法。 该装置包括堆叠，其包括穿透绝缘图案的垂直沟道结构和彼此交替重复堆叠的栅电极。 每个栅极电极包括第一和第二栅极导电层。 在堆叠的外侧和垂直沟道结构之间的第一区域中，第一栅极导电层与垂直沟道结构相邻并且包括截头端部，第二栅极导电层具有与垂直沟道结构相邻的部分 并且被第一栅极导电层中的相应一个和未被第一栅极导电层覆盖的相对部分覆盖。 在垂直沟道结构之间的第二区域中，第一栅极导电层可以被延伸以连续地覆盖第二栅极导电层的表面。

    Semiconductor memory devices and methods of forming the same
    4.
    发明授权
    Semiconductor memory devices and methods of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US08592873B2

    公开(公告)日：2013-11-26

    申请号：US13167858

    申请日：2011-06-24

    申请人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    发明人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.

    摘要翻译： 可以提供半导体器件及其形成方法。 半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。 半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。 半导体器件还可以包括从衬底延伸穿过区域的沟道结构。 通道结构可以包括具有第一形状的第一通道图案。 第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。 通道结构还可以包括具有第二形状的第二通道图案。 第二沟道图案可以包括通孔区域中的第二半导体区域。 第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

    Methods of Forming a Semiconductor Device
    6.
    发明申请
    Methods of Forming a Semiconductor Device 有权
    形成半导体器件的方法

    公开(公告)号：US20130115761A1

    公开(公告)日：2013-05-09

    申请号：US13724632

    申请日：2012-12-21

    申请人： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

    发明人： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

    IPC分类号： H01L21/04

    CPC分类号： H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

    摘要翻译： 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

    Method for fabricating rewritable three-dimensional memory device
    7.
    发明授权
    Method for fabricating rewritable three-dimensional memory device 有权
    可重写三维存储器件的制造方法

    公开(公告)号：US08329537B2

    公开(公告)日：2012-12-11

    申请号：US12816155

    申请日：2010-06-15

    申请人： JinGyun Kim ,  Myoungbum Lee

    发明人： JinGyun Kim ,  Myoungbum Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/30 ,  H01L21/321 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578

    摘要： A method for fabricating a three-dimensional semiconductor memory device including three-dimensionally arranged transistors includes forming a thin film structure comprising a plurality of thin films on a semiconductor substrate, patterning the thin film structure such that a penetration region is formed to expose the semiconductor substrate, forming a polycrystalline semiconductor layer to cover the resultant structure where the penetration region is formed, patterning the semiconductor layer to locally form a semiconductor pattern within the penetration region, and performing a post-treatment process to treat the semiconductor layer or the semiconductor pattern with a post-treatment material containing hydrogen or deuterium.

    摘要翻译： 一种制造包括三维布置晶体管的三维半导体存储器件的方法，包括在半导体衬底上形成包括多个薄膜的薄膜结构，对薄膜结构进行图案化，以形成穿透区域以使半导体 基板，形成多晶半导体层以覆盖其中形成穿透区域的结构，图案化半导体层以在穿透区域内局部形成半导体图案，并执行后处理工艺以处理半导体层或半导体图案 含有氢或氘的后处理材料。

    Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same
    8.
    发明申请
    Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same 审中-公开
    三维半导体存储器件及其形成方法

    公开(公告)号：US20110248327A1

    公开(公告)日：2011-10-13

    申请号：US13039043

    申请日：2011-03-02

    申请人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang ,  Seungjae Baik ,  Jung Ho Kim

    发明人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang ,  Seungjae Baik ,  Jung Ho Kim

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

    摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

    摘要翻译： 非易失性存储器件包括在衬底上的一串非易失性存储器单元。 这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。 第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。 非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。 在衬底中提供连接掺杂半导体区域。 该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。