公开(公告)号：US11314911B1

公开(公告)日：2022-04-26

申请号：US17331835

申请日：2021-05-27

Applicant: Xilinx, Inc.

Inventor： Fangqing Du ,  Sheng Wang ,  Alain Darte ,  Alexandre Isoard ,  Hem C. Neema ,  Lin-Ya Yu

IPC: G06F30/327 ,  G06F30/337

Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.

公开(公告)号：US10956241B1

公开(公告)日：2021-03-23

申请号：US15848691

申请日：2017-12-20

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Soren T. Soe ,  Stephen P. Rozum ,  Nik Cimino

IPC: G06F8/41 ,  G06F9/54 ,  G06F21/57 ,  G06F21/53 ,  G06F8/65

Abstract: A computer program product can include a non-transitory computer readable storage medium storing a unified container. The unified container can include a header structure, wherein the header structure has a fixed length and specifies a number of section headers included in the unified container. The unified container can include a plurality of section headers equivalent to the number of section headers specified in the header structure. The unified container can include a plurality of data sections corresponding to the plurality of section headers on a one-to-one basis. The plurality of data sections includes a first data section including a hardware binary and a second data section including a software binary. The hardware binary and the software binary are configured to program a programmable integrated circuit. Each section header specifies a type of data stored in the corresponding data section and specifies a mapping for the corresponding data section.

公开(公告)号：US10922068B1

公开(公告)日：2021-02-16

申请号：US16186204

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Ryan F. Radjabi ,  Hem C. Neema ,  Sonal Santan ,  Yenpang Lin

IPC: G06F9/44 ,  G06F8/65 ,  G06F13/42

Abstract: Updating firmware in an programmable integrated circuit (IC) includes determining, using a processor of a computer, a base address register (BAR) of an accelerator card from a device data file, wherein the accelerator card includes a programmable IC and is connected to the computer via a communication bus, mapping, using the processor, a feature PROM and a flash programmer circuit of the programmable IC to local memory of the computer using the BAR, and reading, over the communication bus, the feature PROM on the programmable IC to determine a programming mode for programming an external flash memory coupled to the flash programmer circuit. Based on the programming mode and using the processor, firmware is provided to the flash programmer circuit on the programmable IC via the communication bus. The flash programmer circuit is configured to program the firmware into the external flash memory.

公开(公告)号：US20240176936A1

公开(公告)日：2024-05-30

申请号：US18059348

申请日：2022-11-28

Applicant: Xilinx, Inc.

Inventor： Lin-Ya Yu ,  Alexandre Isoard ,  Hem C. Neema

IPC: G06F30/327

CPC classification number: G06F30/327

Abstract: Implementing burst transfers for predicated accesses in high-level synthesis includes generating, using computer hardware, an intermediate representation of a design specified in a high-level programming language. The design is for an integrated circuit. Using the computer hardware, loop predicate information for one or more conditional statements within a loop body of the intermediate representation is determined. A plurality of memory accesses of the loop body guarded by the one or more conditional statements are determined to be sequential memory accesses based on the predicate information. The intermediate representation is modified by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.

公开(公告)号：US20230032302A1

公开(公告)日：2023-02-02

申请号：US17385261

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Luciano Lavagno ,  Xin Jin ,  Dan Liu ,  Thomas Bollaert ,  Hem C. Neema ,  Chaosheng Shi

IPC: G06F9/52 ,  G06F30/20 ,  G06F5/06

Abstract: Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.

公开(公告)号：US10713404B1

公开(公告)日：2020-07-14

申请号：US16218133

申请日：2018-12-12

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Anurag Dubey ,  Pramod Chandraiah ,  Stephen P. Rozum ,  Hem C. Neema

IPC: G06F30/00 ,  G06F30/34 ,  G06F11/36 ,  G06F9/445

Abstract: Embodiments herein describe reconfigurable integrated circuits (ICs) which include programmable logic that can be configured to perform a user task. In one embodiment, the programmable logic is configured as an accelerator. The user may want to gather debug data or profiling data when executing the accelerator. Rather than using debug/profile circuitry disposed in a static region of the IC, the user can provide preferences to a linker which then dynamically configures debug/profile circuitry in a dynamic region of the IC. That is, based on user preferences, the linker can generate customized debug/profile circuitry for monitoring the performance of the accelerator. In one embodiment, the debug/profile circuitry is implemented in the dynamic region of the IC and is tailored to user preferences rather than relying on static, or fixed, debug/profile circuitry. Moreover, the user can retrieve the debug/profiling data on demand using a call back and a device driver.

公开(公告)号：US10802995B2

公开(公告)日：2020-10-13

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F9/38 ,  G06F13/16 ,  G06F9/46 ,  G06F12/0873 ,  G06F12/1045 ,  G06F12/1081

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

公开(公告)号：US20200081850A1

公开(公告)日：2020-03-12

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F13/16 ,  G06F12/1045 ,  G06F12/0873 ,  G06F12/1081 ,  G06F9/46

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

公开(公告)号：US11474555B1

公开(公告)日：2022-10-18

申请号：US15684035

申请日：2017-08-23

Applicant: Xilinx, Inc.

Inventor： Hem C. Neema ,  Sonal Santan ,  Julian M. Kain ,  Stephen P. Rozum ,  Khang K. Dao ,  Kyle Corbett

IPC: G06F1/10 ,  G06F13/10 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

公开(公告)号：US11238199B1

公开(公告)日：2022-02-01

申请号：US17116720

申请日：2020-12-09

Applicant: Xilinx, Inc.

Inventor： Alexandre Isoard ,  Lin-Ya Yu ,  Hem C. Neema

IPC: G06F30/30 ,  G06F30/327 ,  G06F30/323 ,  G06F16/22 ,  G06F111/20

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.