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    SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION
    2.
    发明申请
    SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION 审中-公开

    公开(公告)号：US20200091713A1

    公开(公告)日：2020-03-19

    申请号：US16136104

    申请日：2018-09-19

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

    IPC: H02H9/04 ,  H03K17/693

    Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contract pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

    Selection of logic paths for redundancy
    3.
    发明授权
    Selection of logic paths for redundancy 有权
    选择冗余的逻辑路径

    公开(公告)号：US09484919B1

    公开(公告)日：2016-11-01

    申请号：US14266547

    申请日：2014-04-30

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Pierre Maillard ,  James Karp ,  Michael J. Hart

    IPC: H03K19/003

    CPC classification number: H03K19/00392

    Abstract: Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

    Abstract translation: 公开了用于处理电路设计以防止单个事件扰乱的方法。 基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。 电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。 修改后的电路设计存储在存储器中。

    Single event latch-up (SEL) mitigation techniques
    5.
    发明授权
    Single event latch-up (SEL) mitigation techniques 有权

    公开(公告)号：US10861848B2

    公开(公告)日：2020-12-08

    申请号：US16110894

    申请日：2018-08-23

    Applicant: Xilinx, Inc.

    Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

    IPC: H01L27/06 ,  H01L27/02 ,  H01L49/02 ,  H01L29/73 ,  H01L29/78

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES
    6.
    发明申请
    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES 审中-公开

    公开(公告)号：US20200066837A1

    公开(公告)日：2020-02-27

    申请号：US16109273

    申请日：2018-08-22

    Applicant: Xilinx, Inc.

    Inventor： James Karp ,  Michael J. Hart

    IPC: H01L29/06 ,  H01L27/06 ,  H01L27/092

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

    SINGLE RETICLE APPROACH FOR MULTIPLE PATTERNING TECHNOLOGY
    7.
    发明申请
    SINGLE RETICLE APPROACH FOR MULTIPLE PATTERNING TECHNOLOGY 审中-公开
    多模式技术的单一方法

    公开(公告)号：US20140205934A1

    公开(公告)日：2014-07-24

    申请号：US13746017

    申请日：2013-01-21

    Applicant: Xilinx, Inc.

    Inventor： Toshiyuki Hisamura ,  Michael J. Hart

    IPC: G03F7/20 ,  G03F1/00

    CPC classification number: G03F7/2022 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

    Abstract: A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern.

    Abstract translation: 用于多层图案化集成电路管芯层的掩模版包括具有第一布局图案的第一部分，用于对集成电路管芯的层进行多个图案化，以及具有第二布局图案的第二部分，用于对集成电路的层进行多个图案化 死。 第一布局模式与第二布局模式不同。

    Integrated circuit devices and methods of designing and producing integrated circuits
    8.
    发明授权
    Integrated circuit devices and methods of designing and producing integrated circuits 有权

    公开(公告)号：US10962588B1

    公开(公告)日：2021-03-30

    申请号：US16041412

    申请日：2018-07-20

    Applicant: Xilinx, Inc.

    Inventor： Michael J. Hart

    IPC: G01R31/28 ,  G06F30/20 ,  G06F30/34

    Abstract: A device comprising a plurality of transistors; interconnect elements coupled to the plurality of transistors is described. The interconnect elements enable the transfer of signals between the plurality of transistors. The device further includes a cooling element associated with the device, wherein the cooling element is configured to maintain a temperature of a circuit having the plurality of transistors and interconnect elements below a predetermined temperature; wherein one or more parameters of the device is optimized to operate at a temperature below the predetermined temperature. A method of implementing a circuit is also described.

    Single event latch-up (SEL) mitigation detect and mitigation
    9.
    发明授权
    Single event latch-up (SEL) mitigation detect and mitigation 有权

    公开(公告)号：US10958067B2

    公开(公告)日：2021-03-23

    申请号：US16136104

    申请日：2018-09-19

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

    IPC: H02H9/04 ,  H03K17/693 ,  H02H5/00

    Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

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