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1.发明申请公开(公告)号：US20140346651A1
公开(公告)日：2014-11-27
申请号：US13899129
申请日：2013-05-21
Applicant: Xilinx, Inc.
Inventor： Qi Xiang , Xiao-Yu Li , Cinti X. Chen , Glenn O'Rourke
CPC classification number: H01L23/60 , H01L21/82 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/071 , H01L25/072 , H01L25/18 , H01L2924/181 , H01L2924/00
Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.
Abstract translation: 公开了一般涉及插入件的装置。 在这种装置中，插入器具有多个导体和多个电荷吸引结构。 多个电荷吸引结构是保护至少一个集成电路管芯，以耦合到插入器以提供堆叠的管芯。 多个导体包括多个贯通基板通路。
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公开(公告)号：US09372956B1
公开(公告)日：2016-06-21
申请号：US14537295
申请日：2014-11-10
Applicant: Xilinx, Inc.
Inventor： Yuezhen Fan , Eric J. Thorne , Xiao-Yu Li , Glenn O'Rourke , Stephen M. Trimberger
CPC classification number: G06F17/5081 , G06F17/5054
Abstract: A method of enabling the use of a programmable device having impaired circuitry includes determining one or more locations of the impaired circuitry of the programmable device; generating a defect map for the programmable device based on the determined locations of the impaired circuitry; generating a plurality of configuration bitstreams to implement a circuit in the programmable device; selecting one of the plurality of configuration bitstreams that does not use the impaired circuitry indicated by the defect map; and programming the programmable device with the selected configuration bitstream.
Abstract translation: 能够使用具有受损电路的可编程设备的方法包括确定可编程设备的受损电路的一个或多个位置; 基于所确定的受损电路的位置，生成可编程设备的缺陷图; 生成多个配置比特流以实现可编程设备中的电路; 选择不使用由缺陷图指示的受损电路的多个配置比特流中的一个; 以及使用所选择的配置比特流对可编程设备进行编程。
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公开(公告)号：US09000490B2
公开(公告)日：2015-04-07
申请号：US13866893
申请日：2013-04-19
Applicant: Xilinx, Inc.
Inventor： Thao H. T. Vo , Andy H. Gan , Xiao-Yu Li , Matthew H. Klein
IPC: G06F1/32 , H01L25/065 , G06F17/50
CPC classification number: H01L25/0652 , G06F1/3203 , G06F1/324 , G06F17/5045 , G06F17/5054 , H01L25/0655 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2224/05552
Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.
Abstract translation: 半导体封装包括插入件和多个集成电路（IC）芯片，其经由插入器设置并耦合。 第一个IC芯片的时钟速度等级大于另一个IC芯片的时钟速度等级。 多个可编程电压调谐器分别耦合到多个IC芯片。 第一电压调谐器耦合到第一IC芯片，并且第一电压调谐器被编程以降低输入到第一电压调谐器的电压的电压电平，并将降低的电压输出到第一IC芯片。
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4.发明授权Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product 有权用于在硅堆叠互连技术（SSIT）产品中跟踪插入器裸片的方法和装置公开(公告)号：US08987009B1
公开(公告)日：2015-03-24
申请号：US13742010
申请日：2013-01-15
Applicant: Xilinx, Inc.
Inventor： Cinti X. Chen , Myongseob Kim , Xiao-Yu Li , Mohsen H. Mardi
IPC: H01L21/71 , H01L21/98 , H01L21/673 , H01L21/66 , H01L23/00
CPC classification number: H01L25/0655 , H01L22/26 , H01L23/147 , H01L23/49827 , H01L23/49838 , H01L23/544 , H01L24/17 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54486 , H01L2223/54493 , H01L2224/13124 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/1712 , H01L2224/17515 , H01L2924/01013 , H01L2924/14 , H01L2924/15311
Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.
Abstract translation: 一种用于跟踪堆叠硅互连技术（SSIT）产品的插入器管芯的方法包括在插入器管芯上形成多个虚拟部件，并修改插入器管芯上的多个虚拟部件中的一个或多个，以形成唯一的标识符 内插器死亡。 叠层硅互连技术（SSIT）产品的装置包括插入器裸片和插入器裸片上的多个虚拟部件。 多个虚拟部件中的一个或多个可修改以形成用于插入器裸片的唯一标识符。
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Patent Agency Ranking
公开(公告)号：US20140312483A1
公开(公告)日：2014-10-23
申请号：US13866893
申请日：2013-04-19
Applicant: Xilinx, Inc.
Inventor： Thao H.T. Vo , Andy H. Gan , Xiao-Yu Li , Matthew H. Klein
IPC: H01L25/065
CPC classification number: H01L25/0652 , G06F1/3203 , G06F1/324 , G06F17/5045 , G06F17/5054 , H01L25/0655 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2224/05552
Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.
Abstract translation: 半导体封装包括插入件和多个集成电路（IC）芯片，其经由插入器设置并耦合。 第一个IC芯片的时钟速度等级大于另一个IC芯片的时钟速度等级。 多个可编程电压调谐器分别耦合到多个IC芯片。 第一电压调谐器耦合到第一IC芯片，并且第一电压调谐器被编程以降低输入到第一电压调谐器的电压的电压电平，并将降低的电压输出到第一IC芯片。
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公开(公告)号：US11762958B1
公开(公告)日：2023-09-19
申请号：US16591179
申请日：2019-10-02
Applicant: XILINX, INC.
Inventor： Ran Zhou , Cinti X. Chen , Xiao-Yu Li
CPC classification number: G06F18/295 , G01R31/2831 , G06F30/34 , G06N20/00
Abstract: Examples described herein provide for determining a recipe for identifying from which buckets integrated circuit chips are taken to form units of a multi-chip apparatus. In an example, a method uses a processor-based system and uses a Markov Decision Process. Buckets are defined based on respective characteristics of manufactured chips. Each of the manufactured chips is binned into a respective one of the buckets based on the characteristic of the respective manufactured chip. A recipe for identifying from which of the buckets to take one or more of the manufactured chips to incorporate into respective ones of the units of the multi-chip apparatus is generated.
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公开(公告)号：US10707138B1
公开(公告)日：2020-07-07
申请号：US15473395
申请日：2017-03-29
Applicant: Xilinx, Inc.
Inventor： Shiying Xiong , Thao H. T. Vo , Felino E. Pagaduan , Qi Xiang , Xiao-Yu Li , Glenn O'Rourke
Abstract: An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.
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8.发明授权Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product 有权用于在硅堆叠互连技术（SSIT）产品中跟踪插入器裸片的方法和装置公开(公告)号：US09236367B1
公开(公告)日：2016-01-12
申请号：US14625145
申请日：2015-02-18
Applicant: Xilinx, Inc.
Inventor： Cinti X. Chen , Myongseob Kim , Xiao-Yu Li , Mohsen H. Mardi
IPC: H01L27/12 , H01L25/00 , H01L23/544 , H01L25/065 , H01L23/00 , H01L23/498
CPC classification number: H01L25/0655 , H01L22/26 , H01L23/147 , H01L23/49827 , H01L23/49838 , H01L23/544 , H01L24/17 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54433 , H01L2223/54486 , H01L2223/54493 , H01L2224/13124 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/1712 , H01L2224/17515 , H01L2924/01013 , H01L2924/14 , H01L2924/15311
Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.
Abstract translation: 一种用于叠层硅互连技术（SSIT）产品的装置，包括插入器管芯，多个集成电路管芯，在集成电路管芯和内插管芯之间形成有源连接的多个有源部件，以及多个虚设部件 插入器裸片，虚设部件不形成集成电路管芯和内插器管芯之间的有源连接。 虚拟部件的至少一个子集形成图案，并且图案包括插入器裸片的标识符。
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9.发明授权公开(公告)号：US09214433B2
公开(公告)日：2015-12-15
申请号：US13899129
申请日：2013-05-21
Applicant: Xilinx, Inc.
Inventor： Qi Xiang , Xiao-Yu Li , Cinti X. Chen , Glenn O'Rourke
IPC: H01L23/552 , H01L23/60 , H01L21/82 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/00
CPC classification number: H01L23/60 , H01L21/82 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/071 , H01L25/072 , H01L25/18 , H01L2924/181 , H01L2924/00
Abstract: An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.
Abstract translation: 公开了一般涉及插入件的装置。 在这种装置中，插入器具有多个导体和多个电荷吸引结构。 多个电荷吸引结构是保护至少一个集成电路管芯，以耦合到插入器以提供堆叠的管芯。 多个导体包括多个贯通基板通路。
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