公开(公告)号：US20130307137A1

公开(公告)日：2013-11-21

申请号：US13898300

申请日：2013-05-20

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Yu-Min LIANG

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L23/498 ,  B81B7/0077 ,  H01L21/78 ,  H01L24/94 ,  H01L27/14618 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.

Abstract translation: 本发明的实施例提供了一种芯片封装，包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述第一表面上的电介质层; 以及导电焊盘结构，其设置在所述电介质层中并电连接到所述器件区域; 设置在所述芯片和所述盖基板之间的覆盖基板，其中所述间隔层，空腔由所述芯片和所述器件区域上的覆盖基板所围绕，并且所述间隔层与所述芯片直接接触而没有任何粘合胶 设置在芯片和间隔层之间。

公开(公告)号：US20250054849A1

公开(公告)日：2025-02-13

申请号：US18779105

申请日：2024-07-22

Applicant: Xintec Inc.

Inventor： Wei-Luen SUEN ,  Po-Jung CHEN ,  Chia-Ming CHENG ,  Po-Shen LIN ,  Jiun-Yen LAI ,  Tsang-Yu LIU ,  Shu-Ming CHANG

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/15 ,  H01L23/528

Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

公开(公告)号：US20170186712A1

公开(公告)日：2017-06-29

申请号：US15393170

申请日：2016-12-28

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Po-Shen LIN ,  Ang CHAN

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/31

Abstract: A chip package including a substrate is provided. The substrate includes a front surface, a back surface, and a side surface. A redistribution layer is disposed on the back surface and is electrically connected to a sensing or device region in the substrate. A protection layer covers the redistribution layer and extends onto the side surface. A cover plate is disposed on the front surface and laterally protrudes from the protection layer on the side surface. The cover plate includes a first surface facing the front surface and a second surface facing away from the front surface. A bottom portion of the cover plate broadens from the first surface towards the second surface. A method of forming the chip package is also provided.

公开(公告)号：US20160049436A1

公开(公告)日：2016-02-18

申请号：US14819348

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A colour filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the colour filter. The carrier substrate is removed.

Abstract translation: 制造芯片封装的方法包括提供至少具有光电二极管和互连层的半导体衬底。 互连层设置在半导体衬底的上表面上并且在光电二极管之上并且电连接到光电二极管。 至少在互连层上形成再分布电路。 再分配电路电连接到互连层。 在再分配电路上形成封装层。 随后，将载体衬底附接到包装层。 滤色器形成在半导体衬底的下表面上。 在滤色器下方形成微透镜模块。 移除载体衬底。

公开(公告)号：US20140251946A1

公开(公告)日：2014-09-11

申请号：US14282457

申请日：2014-05-20

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  I-Min LIN ,  Po-Shen LIN

IPC: H05K3/06

CPC classification number: H05K3/06 ,  H01L21/4853 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract translation: 提供了一种用于改善冠状缺陷的布线结构及其制造方法。 该方法包括以下步骤。 提供了其上形成有种子层和具有开口的图案化光致抗蚀剂层的衬底。 在开口中形成有覆盖种子层的底部的铜层。 覆盖铜层的至少一个顶部的阻挡层形成在铜层上。 阻挡层的氧化电位大于铜层的氧化电位。 去除图案化的光致抗蚀剂层以进行蚀刻工艺，其中铜层和暴露的种子层的一部分被蚀刻以形成布线层。 进行浸渍处理以在阻挡层和布线层的暴露表面上综合地形成抗氧化层。

公开(公告)号：US20130341747A1

公开(公告)日：2013-12-26

申请号：US13921999

申请日：2013-06-19

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Shih-Chin CHEN

IPC: H01L31/0232 ,  H01L31/02

CPC classification number: H01L31/0232 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/02 ,  H01L31/02327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：芯片，包括：具有第一表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 以及在所述第一表面和所述器件区域上的多个微透镜; 设置在所述芯片上的盖基板，其中所述盖基板为透明基板; 设置在所述芯片和所述覆盖基板之间的间隔层，其中所述间隔层，所述芯片和所述覆盖基板一起围绕所述器件区域中的空腔; 以及在所述盖基板上和所述空腔中的至少一个主透镜，其中所述主透镜的宽度大于每个所述微透镜的宽度。