公开(公告)号：US06352919B1

公开(公告)日：2002-03-05

申请号：US09620033

申请日：2000-07-20

申请人： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

发明人： Yeur-Luen Tu ,  Bor-Wen Chan ,  Yuan-Hung Liu

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  H01L21/76801

摘要： A method of fabricating a borderless via is disclosed. A semiconductor substrate having a first dielectric layer thereon is provided. Next, a first conductive structure and a second conductive structure whose area is much smaller than said first conductive structure are formed on said first dielectric layer. After that, a second dielectric layer with an uneven surface is formed. Then, a planarizing layer is coated over said second dielectric layer to fill said uneven surface. Next, an etch back process is used to create a etching stop layer consisting of a portion of second dielectric layer. Subsequently, a third dielectric layer is formed over said second dielectric layer followed by selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.

摘要翻译： 公开了制造无边界通孔的方法。 提供其上具有第一介电层的半导体衬底。 接下来，在所述第一介电层上形成面积比所述第一导电结构小得多的第一导电结构和第二导电结构。 之后，形成具有不平坦表面的第二电介质层。 然后，在所述第二电介质层上涂覆平坦化层以填充所述不平坦表面。 接下来，使用回蚀工艺来产生由第二介电层的一部分组成的蚀刻停止层。 随后，在所述第二电介质层上形成第三电介质层，随后选择性地蚀刻所述第三电介质层，直到所述第二电介质层暴露以形成无边界通孔。

公开(公告)号：US06399286B1

公开(公告)日：2002-06-04

申请号：US09384013

申请日：1999-08-26

申请人： Yuan-Hung Liu ,  Bor-Wen Chan

发明人： Yuan-Hung Liu ,  Bor-Wen Chan

IPC分类号： G03F736

CPC分类号： H01L21/32139 ,  H01L21/76838 ,  H01L23/53214 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.

摘要翻译： 描述了用于降低导电线的临界尺寸和空间的制造方法，其中导电层和掩模层依次形成在基板上。 进行锥形蚀刻以形成多个第一开口，其中开口的横截面从顶部到底部逐渐变细，并暴露导电层的表面。 形成与掩模层类似的高度的平坦化牺牲层，覆盖导电层的暴露表面。 在暴露的掩模层上进一步进行第二锥形腐蚀以形成多个第二开口，其中开口的横截面从顶部到底部逐渐变细。 然后去除牺牲层。 此后，使用掩模层作为硬掩模，在暴露的导电层上进行各向异性蚀刻，以形成多条导线，然后除去掩模层。

公开(公告)号：US06218244B1

公开(公告)日：2001-04-17

申请号：US09482757

申请日：2000-01-13

申请人： Bor-Wen Chan ,  Yuan-Hung Liu

发明人： Bor-Wen Chan ,  Yuan-Hung Liu

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L27/10852

摘要： A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.

摘要翻译： 描述制造DRAM电容器的方法。 硅衬底结构包括在衬底上的氧化物层和氧化物层上的多晶硅层。 多晶硅层还包括穿透氧化物层的插塞。 随后在多晶硅层上形成图案化的光致抗蚀剂层。 通过在光致抗蚀剂层的侧壁附近进行化学反应，在光致抗蚀剂层的侧壁上形成具有低蚀刻速率的间隔物。 进行干蚀刻操作以蚀刻由光致抗蚀剂层中的开口暴露的未反应的光致抗蚀剂层和多晶硅层。 使用间隔物作为蚀刻掩模，通过继续干蚀刻操作来除去光致抗蚀剂层下面的多晶硅层的一部分。 最后，去除间隔物以形成冠状电容器。

公开(公告)号：US06291312B1

公开(公告)日：2001-09-18

申请号：US09395108

申请日：1999-09-14

申请人： Bor-Wen Chan ,  Yuan-Hung Liu

发明人： Bor-Wen Chan ,  Yuan-Hung Liu

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

摘要翻译： 一种用于在浅沟槽隔离结构上形成回拉开口的方法。 在衬底上形成图案化掩模层。 牺牲层形成在掩模层的侧壁上。 蚀刻衬底的暴露部分以在衬底中形成沟槽。 去除牺牲层以增加沟槽上方的开口的宽度。

公开(公告)号：US06232175B1

公开(公告)日：2001-05-15

申请号：US09466044

申请日：1999-12-17

申请人： Yuan-Hung Liu ,  Bor-Wen Chan

发明人： Yuan-Hung Liu ,  Bor-Wen Chan

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L21/32139 ,  H01L27/10852

摘要： A double recess crown-shaped DRAM capacitor is formed in a simplified process. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed. Using the triangular-shaped dielectric layers as a hard etching mask, two types of trenches each having a different depth are formed in the conductive layer. The triangular-shaped dielectric layers are removed to form a double-recess lower electrode. Hemispherical silicon grains are grown over the interior surface of the double-recess lower electrode as well as the external sidewalls. Finally, a conformal dielectric layer and a conformal conductive layer are sequentially formed over the surface of the double-recess lower electrode.

摘要翻译： 以简化的工艺形成双凹槽冠状DRAM电容器。 介电层形成在衬底上。 使用光刻和蚀刻技术，在电介质层中形成接触开口。 在填充接触开口的电介质层上形成导电层以形成导电插塞。 在导电层上形成第二介电层。 再次使用光刻和蚀刻技术，将第二介电层图案化以形成梯形介电层。 将有机底部抗反射涂层（有机BARC）涂覆在梯形介电层和导电层上。 去除梯形介电层上方的有机BARC。 使用有机BARC作为蚀刻掩模，蚀刻梯形介电层以在导电层中形成三角形介电层和沟槽。 残留的有机BARC被完全去除。 使用三角形介电层作为硬蚀刻掩模，在导电层中形成各具有不同深度的两种类型的沟槽。 去除三角形电介质层以形成双凹槽下电极。 半球状硅晶粒生长在双凹槽下电极的内表面以及外侧壁上。 最后，在双凹槽下电极的表面上依次形成保形电介质层和保形导电层。

公开(公告)号：US08513107B2

公开(公告)日：2013-08-20

申请号：US12693504

申请日：2010-01-26

申请人： Bor-Wen Chan ,  Fang Wen Tsai

发明人： Bor-Wen Chan ,  Fang Wen Tsai

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.

摘要翻译： 提供了用于替代金属栅极技术的结构和方法，用于与半导体鳍片或其它器件结合使用。 通过去除诸如多晶硅的牺牲栅极材料在电介质中形成开口。 在其中形成晶体管沟道的半导体鳍片的表面在开口中露出。 通过在开口内部和栅极电介质材料上形成扩散阻挡层形成替代金属栅极，扩散阻挡层形成有利地进行原位等离子体处理操作。 处理操作利用氩和氢中的至少一种，并固化扩散阻挡层中的表面缺陷，使得扩散阻挡层能够形成较小的厚度。 处理操作降低电阻率，致密化并改变扩散阻挡层的原子比，随后进行金属沉积。

公开(公告)号：US20110027958A1

公开(公告)日：2011-02-03

申请号：US12904809

申请日：2010-10-14

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/336

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US07241674B2

公开(公告)日：2007-07-10

申请号：US10846278

申请日：2004-05-13

申请人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC分类号： H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

摘要翻译： 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20060040481A1

公开(公告)日：2006-02-23

申请号：US10919571

申请日：2004-08-17

申请人： Bor-Wen Chan ,  Yu-Shen Lai

发明人： Bor-Wen Chan ,  Yu-Shen Lai

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L29/66507 ,  H01L29/6656

摘要： Methods and structures for preventing salicidation are disclosed. A substrate has an gate electrode on it. Spacers are on sidewalls of the gate electrode, exposing a top portion of the gate electrode. A dielectric layer is formed above the spacers, covering the exposed top portion of the gate electrode. Methods and structures for forming source and drain salicidation are disclosed. They further salicidize source and drain regions which are adjacent to the spacers without forming salicidation on the gate electrode while salicidizing the source and drain regions. Methods and structures for forming gate electrode salicidation are also disclosed. They further form another dielectric layer covering the salicidized source and drain regions. A portion of the dielectric layer is removed so as to expose a top surface of the gate electrode. The gate electrode is then salicidized.

摘要翻译： 公开了防止盐化的方法和结构。 衬底上具有栅电极。 隔板位于栅电极的侧壁上，露出栅电极的顶部。 在间隔物的上方形成介电层，覆盖露出的栅电极顶部。 公开了用于形成源极和漏极盐析的方法和结构。 它们进一步对与间隔物相邻的源极和漏极区域进行盐化，而不会在栅电极上形成水化，同时对源极和漏极区域进行盐化。 还公开了形成栅电极盐析的方法和结构。 它们进一步形成覆盖水化源极和漏极区域的另一个介电层。 去除电介质层的一部分以露出栅电极的顶表面。 然后将栅电极进行水杨酸化。

公开(公告)号：US20050179098A1

公开(公告)日：2005-08-18

申请号：US10780513

申请日：2004-02-17

申请人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

摘要翻译： 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。