公开(公告)号：US08508999B2

公开(公告)日：2013-08-13

申请号：US13451656

申请日：2012-04-20

申请人： Zengtao Liu ,  Graham Wolstenholme

发明人： Zengtao Liu ,  Graham Wolstenholme

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582

摘要： A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations.

摘要翻译： 垂直NAND结构包括具有至少两个功能模式的一个或多个中串式装置。 在第一模式中，一个或多个中串式装置将NAND存储器单元堆叠的主体耦合到衬底以进行擦除操作。 在第二模式中，一个或多个中串装置将第一堆NAND存储器单元的主体耦合到第二堆存储器NAND存储器单元的主体，允许两个堆作为单个NAND串用于读取和 编程操作。

公开(公告)号：US20120012921A1

公开(公告)日：2012-01-19

申请号：US12836853

申请日：2010-07-15

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/088 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

公开(公告)号：US07259984B2

公开(公告)日：2007-08-21

申请号：US10718662

申请日：2003-11-24

申请人： Edwin C. Kan ,  Zengtao Liu ,  Chungho Lee

发明人： Edwin C. Kan ,  Zengtao Liu ,  Chungho Lee

IPC分类号： G11C11/34

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06

摘要： Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid thermal annealing of ultra thin metal film deposited on top of gate oxide is integrated with NMOSFET to fabricate such devices. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime, with hot-carrier injection as the programming mechanism, demonstrate retention times up to 106s, and provide 2-bit-per-cell storage capability.

摘要翻译： 金属纳米晶体存储器被制造成包括比半导体纳米晶体器件可用的更高密度状态，更强的与沟道的耦合以及更好的尺寸可扩展性。 通过沉积在栅极氧化物顶部的超薄金属膜的快速热退火的自组装纳米晶体形成工艺与NMOSFET集成以制造这种器件。 具有在FN隧穿状态下工作的Au，Ag和Pt纳米晶体的器件以热载流子注入作为编程机制，证明保留时间高达10 6，并提供2位/ 细胞储存能力。

公开(公告)号：US20060216922A1

公开(公告)日：2006-09-28

申请号：US11407429

申请日：2006-04-20

申请人： Luan Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

公开(公告)号：US20120182805A1

公开(公告)日：2012-07-19

申请号：US13006762

申请日：2011-01-14

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L21/336

CPC分类号： G11C16/0491 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11517 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

摘要翻译： 具有字符串选择栅的存储单元串被配置成同时选择性地将字符串的端部耦合到数据线和源极线，提供包含这种字符串的存储器件以及用于访问和形成这种字符串的方法。 例如，公开了利用串行连接的非易失性存储器单元的垂直结构NAND串的非易失性存储器件。 一种这样的串包括两个或多个串联的非易失性存储单元，其中串的每一端与串的另一端共享串选择门。

公开(公告)号：US20110299328A1

公开(公告)日：2011-12-08

申请号：US12795565

申请日：2010-06-07

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： G11C11/00

CPC分类号： G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

摘要翻译： 一些实施例包括存储器阵列。 存储器阵列可以具有沿着第一水平方向延伸的全局位线，垂直于全局位线垂直延伸的垂直局部位线以及沿垂直于第一水平方向的第二水平方向延伸的字线。 全局位线可以在第一高度级细分为第一系列，而在第二高度级可以被分为与第一高度不同的第二系列。 第一个系列的全局位线可以与第二个系列的全局位线交替。 直接在字线和垂直的局部位线之间可以存储单元格材料。 存储单元材料可以形成由字线/全局位线组合唯一地寻址的多个存储单元。 一些实施例包括具有约2F2的面积的交叉点存储单元单元。

公开(公告)号：US20060291282A1

公开(公告)日：2006-12-28

申请号：US11511763

申请日：2006-08-29

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

公开(公告)号：US07120063B1

公开(公告)日：2006-10-10

申请号：US10841850

申请日：2004-05-07

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US06646302B2

公开(公告)日：2003-11-11

申请号：US09911378

申请日：2001-07-25

申请人： Edwin C. Kan ,  Zengtao Liu ,  Venkatasubraman Narayanan

发明人： Edwin C. Kan ,  Zengtao Liu ,  Venkatasubraman Narayanan

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  H01L21/2855 ,  H01L29/42332

摘要： Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.

公开(公告)号：US09208881B2

公开(公告)日：2015-12-08

申请号：US13993312

申请日：2011-09-22

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： G11C16/02 ,  H01L27/115

CPC分类号： H01L27/11565 ,  G11C16/02 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch. Other embodiments may be described and claimed.

摘要翻译： 本公开的实施例描述了具有不匹配的单元和位线间距的NAND存储器阵列的方法，装置和系统配置。 可以描述和要求保护其他实施例。