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    LOW RESISTANCE VIA CONTACTS IN A MEMORY DEVICE
    2.
    发明申请
    LOW RESISTANCE VIA CONTACTS IN A MEMORY DEVICE 有权

    公开(公告)号：US20250107459A1

    公开(公告)日：2025-03-27

    申请号：US18972316

    申请日：2024-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Giulio Albini

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.

    MICROELECTRONIC DEVICES WITH ACTIVE SOURCE/DRAIN CONTACTS IN TRENCH IN SYMMETRICAL DUAL-BLOCK STRUCTURE, AND RELATED METHODS
    3.
    发明申请
    MICROELECTRONIC DEVICES WITH ACTIVE SOURCE/DRAIN CONTACTS IN TRENCH IN SYMMETRICAL DUAL-BLOCK STRUCTURE, AND RELATED METHODS 有权

    公开(公告)号：US20250107204A1

    公开(公告)日：2025-03-27

    申请号：US18974584

    申请日：2024-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Richard J. Hill ,  Indra V. Chary ,  Lars P. Heineck

    IPC: H01L29/417 ,  H01L21/768 ,  H01L23/528 ,  H01L29/40

    Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

    DUAL-READ DATA INTEGRITY SCAN IN A MEMORY SUB-SYSTEM
    5.
    发明申请
    DUAL-READ DATA INTEGRITY SCAN IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20250104789A1

    公开(公告)日：2025-03-27

    申请号：US18774799

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Hanping Chen ,  Peng Zhang ,  Zhenming Zhou

    IPC: G11C29/12

    Abstract: A processing device in a memory sub-system performs a first data integrity scan on a block of a memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level, and performs, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level. The processing device determines a difference between the first combined reliability statistic and the second combined reliability statistic and, responsive to the difference between the first combined reliability statistic and the second combined reliability statistic satisfying a threshold criterion, performs a corrective action on the block of the memory device.

    PERSISTENT HEALTH MONITORING FOR VOLATILE MEMORY SYSTEMS
    7.
    发明申请
    PERSISTENT HEALTH MONITORING FOR VOLATILE MEMORY SYSTEMS 有权

    公开(公告)号：US20250103416A1

    公开(公告)日：2025-03-27

    申请号：US18909706

    申请日：2024-10-08

    Applicant: Micron Technology, Inc.

    Inventor： Debra M. Bell ,  Kristen M. Hopper ,  Erika Prosser ,  Aaron P. Boehm

    IPC: G06F11/07 ,  G06F1/20 ,  G06F1/30 ,  G06F3/06 ,  G06F11/30

    Abstract: Methods, systems, and devices for persistent health monitoring for volatile memory devices are described. A memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. The memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. In some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. The memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.

    Memory devices and related methods of forming a memory device
    9.
    发明授权
    Memory devices and related methods of forming a memory device 有权

    公开(公告)号：US12261111B2

    公开(公告)日：2025-03-25

    申请号：US18600146

    申请日：2024-03-08

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh

    IPC: H01L23/522 ,  G11C7/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35

    Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

    Loopback datapath for clock quality detection
    10.
    发明授权
    Loopback datapath for clock quality detection 有权

    公开(公告)号：US12260926B2

    公开(公告)日：2025-03-25

    申请号：US18312280

    申请日：2023-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Matthew Alan Prather ,  Won Ho Choi

    IPC: G11C29/12

    Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

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