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    Output Current Monitor Circuit for Switching Regulator
    5.
    发明申请
    Output Current Monitor Circuit for Switching Regulator 有权
    开关稳压器的输出电流监测电路

    公开(公告)号：US20170012527A1

    公开(公告)日：2017-01-12

    申请号：US14795147

    申请日：2015-07-09

    申请人： Dialog Semiconductor (UK) Limited

    发明人： Seiichi Ozawa

    IPC分类号： H02M3/158

    CPC分类号： H02M3/158 ,  H02M3/156 ,  H02M3/1588 ,  H02M2001/0009 ,  H03K5/1536

    摘要： A circuit and method for providing an improved current monitoring circuit for a switching regulator. A circuit providing switching regulation with an improved current monitor, comprising a pulse width modulation (PWM) controller configured to provide P- and N-drive signals, an output stage connected to said PWM controller and configured to provide switching, comprising a high-side and low-side transistor, driven by said P- and N-drive signals, respectively, a sense circuit configured to provide output current sensing from the output stage during a sampling period when the N-drive signal is active, and a sampling timing generator configured to provide a an n-sampling signal, nsample, to the sense circuit, wherein a start of the n-sampling signal is delayed by a first delay after the sampling period and the n-sampling signal is ended prior to an end of the sampling period by a second delay.

    摘要翻译： 一种用于为开关调节器提供改进的电流监测电路的电路和方法。 一种提供具有改进的电流监视器的开关调节的电路，包括被配置为提供P和N驱动信号的脉冲宽度调制（PWM）控制器，连接到所述PWM控制器并被配置为提供切换的输出级，所述输出级包括高侧 和低侧晶体管，分别由所述P驱动信号和N驱动信号驱动，所述感测电路被配置为在所述N驱动信号有效时在采样周期期间从所述输出级提供输出电流感测，以及采样定时发生器 被配置为向所述感测电路提供n采样信号ns采样，其中所述n采样信号的开始在所述采样周期之后延迟第一延迟，并且所述n采样信号在所述采样周期的结束之前结束 采样周期延迟一秒。

    Zero-crossing detection circuit and method for synchronous step-down converter
    6.
    发明授权
    Zero-crossing detection circuit and method for synchronous step-down converter 有权
    用于同步降压转换器的过零检测电路和方法

    公开(公告)号：US09444441B2

    公开(公告)日：2016-09-13

    申请号：US14541428

    申请日：2014-11-14

    申请人： Silergy Semiconductor Technology (Hangzhou) LTD

    发明人： Jinzhao Hou ,  Chen Chen

    IPC分类号： H02M3/158 ,  H03K5/1536

    CPC分类号： H03K5/1536 ,  H02M3/158 ,  H02M3/1588 ,  Y02B70/1466

    摘要： In one embodiment, a zero-crossing detection circuit for a synchronous step-down converter, can include: (i) a state determination circuit configured to compare a drain voltage of a synchronous transistor of the synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of the synchronous transistor is turned on; (ii) a logic circuit configured to convert the state digital signal into a counting instruction signal; (iii) a plus-minus counter configured to generate a numerical signal in response to the counting instruction signal; (iv) a DAC configured to generate a correction analog signal based on the numerical signal; and (v) a zero-crossing comparator configured to receive the correction analog signal and the drain voltage of the synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of the synchronous step-down converter.

    摘要翻译： 在一个实施例中，用于同步降压转换器的过零检测电路可以包括：（i）状态确定电路，被配置为将同步降压转换器的同步晶体管的漏极电压与参考电压进行比较， 并产生指示同步晶体管的体二极管是否导通的状态数字信号; （ii）逻辑电路，被配置为将所述状态数字信号转换为计数指令信号; （iii）正负计数器，被配置为响应于所述计数指令信号产生数字信号; （iv）配置为基于所述数字信号产生校正模拟信号的DAC; 以及（v）配置成接收所述同步晶体管的校正模拟信号和漏极电压的过零比较器，并且向所述同步降压转换器的驱动电路提供过零比较信号。

    Zero-Crossing Voltage Detection Circuit and Method Thereof
    7.
    发明申请
    Zero-Crossing Voltage Detection Circuit and Method Thereof 有权
    过零电压检测电路及其方法

    公开(公告)号：US20160087619A1

    公开(公告)日：2016-03-24

    申请号：US14836950

    申请日：2015-08-26

    申请人： GREEN SOLUTION TECHNOLOGY CO., LTD.

    发明人： Li-Min LEE ,  Chao SHAO

    IPC分类号： H03K5/1536 ,  H03K17/13 ,  H03K5/24

    CPC分类号： H03K5/1536 ,  H03K5/24 ,  H03K5/2409 ,  H03K5/2418 ,  H03K17/13 ,  H03K17/133

    摘要： A zero-crossing voltage detection circuit for detecting a phase voltage of a converter includes a comparator, a first transistor and a second transistor. The first transistor has a first base, a first collector and a first emitter. The first base couples with the first collector. The first emitter receives the phase voltage. The first collector provides a first voltage to a first terminal of the comparator. The second transistor has a second base, a second collector and a second emitter. The second base couples with the first base. The second base couples with the second collector. The second emitter receives a ground voltage. The second collector provides a second voltage to a second terminal of the comparator. The comparator compares the first voltage with the second voltage to generate a zero-crossing voltage signal.

    摘要翻译： 用于检测转换器的相电压的过零电压检测电路包括比较器，第一晶体管和第二晶体管。 第一晶体管具有第一基极，第一集电极和第一发射极。 第一个基地与第一个收藏家。 第一个发射极接收相电压。 第一集电极向比较器的第一端提供第一电压。 第二晶体管具有第二基极，第二集电极和第二发射极。 第二个基地与第一个基地相配。 第二个底座与第二个收集器相连。 第二发射器接收地电压。 第二集电极向比较器的第二端提供第二电压。 比较器比较第一电压和第二电压以产生过零电压信号。

    CIRCUIT AND ARCHITECTURE FOR A DEMODULATOR FOR A WIRELESS POWER TRANSFER SYSTEM AND METHOD THEREFOR
    8.
    发明申请
    CIRCUIT AND ARCHITECTURE FOR A DEMODULATOR FOR A WIRELESS POWER TRANSFER SYSTEM AND METHOD THEREFOR 有权
    一种用于无线电力传输系统的解调器的电路和结构及其方法

    公开(公告)号：US20150171935A1

    公开(公告)日：2015-06-18

    申请号：US14502048

    申请日：2014-09-30

    申请人： Texas Instruments Incorporated

    发明人： Ashish Khandelwal ,  Joseph M. Khayat ,  Yipeng Su ,  Robert A. Neidorff ,  Bharath B. Kannan

    IPC分类号： H04B5/00

    CPC分类号： H02J50/10 ,  H02J5/005 ,  H02J7/025 ,  H02J50/80 ,  H03K5/1532 ,  H03K5/1536 ,  H03K5/24 ,  H03K19/20 ,  H03K2005/00078 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0093 ,  H04B5/02

    摘要： A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

    摘要翻译： 电感耦合到次级侧无线电力接收器的初级侧无线电力发射机用于向无线电力接收器供电以通过电感耦合从次级侧无线电力接收器接收通信包括初级侧电路接收来自次级侧的信号 侧无线电源接收器。 相位延迟或时间延迟电路产生固定的延迟时钟信号。 采样和保持电路利用固定相位或时间延迟的时钟信号对储能电路电压进行采样。 比较器耦合到采样和保持电路的输出端，用于从信号流中提取数据或命令。 还公开了一种操作初级侧无线发射机的方法，所述初级侧无线发射机感应耦合到次级侧无线电力接收机，用于向无线电力接收机供电以为耦合到接收机的负载供电。

    Phase interpolator based output waveform synthesizer for low-power broadband transmitter
    10.
    发明授权
    Phase interpolator based output waveform synthesizer for low-power broadband transmitter 有权
    用于低功率宽带发射机的基于相位插值器的输出波形合成器

    公开(公告)号：US08917116B2

    公开(公告)日：2014-12-23

    申请号：US13843054

    申请日：2013-03-15

    申请人： TeraSquare Co., Ltd.

    发明人： Hyeon Min Bae ,  Tae Hun Yoon ,  Jong Hyeok Yoon

    IPC分类号： H03H11/16

    CPC分类号： H03B21/00 ,  H03K5/1536 ,  H03M9/00 ,  H04L7/0332

    摘要： Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

    摘要翻译： 本发明的示例性实施例涉及一种使用相位内插器的输出波形合成器和用于低功率发射器的片上开眼监测（EOM）电路。 为了在发射机设计中实现小面积和低功耗，采用了以子速率工作的单级多相多路复用器。 多相多路复用器由并联开漏NAND门组成。 在子速率发射机架构中，多相时钟信号之间的相位不匹配会显着降低抖动性能，并且是低功耗的广泛使用的关键瓶颈。 为了克服这种不匹配问题，开发了基于面积和功率的相位插值器的波形合成方案。