公开(公告)号：US20250062772A1

公开(公告)日：2025-02-20

申请号：US18792106

申请日：2024-08-01

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： JIAN-RU LIN ,  YING-CHENG WU ,  YUNG-TAI CHEN ,  JUN-YE WU

IPC: H03M1/00 ,  H03M1/06 ,  H04B1/04 ,  H04L25/02

Abstract: A receiver for wired communication, includes a DC (direct current) level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit is configured to receive a first signal and generate a second signal, in which the DC level shift circuit comprises a capacitor, and the DC level shift circuit is further configured to transmit a first common-mode voltage in a first voltage domain to a first terminal of the capacitor and transmit a second common-mode voltage in a second voltage domain to a second terminal of the capacitor before the first signal is received, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit is configured to generate a digital signal according to the second signal.

公开(公告)号：US12224765B1

公开(公告)日：2025-02-11

申请号：US18194172

申请日：2023-03-31

Applicant: PixArt Imaging Incorporation

Inventor： Boon-Eu Seow ,  Kei-Tee Tiew

IPC: H03M1/18 ,  H03M1/38 ,  H03M1/00 ,  H03M1/12

Abstract: An SAR ADC includes: at least one sub-ADC, configured to convert a corresponding input signal to a corresponding SAR code; and a tuning control unit, configured to adjust a full-scale voltage (VFS) of each of the sub-ADC to a corresponding predetermined target level in a VFS tuning mode. The tuning control unit generates a tuning code to control an adjusting capacitor array coupled to the sub-ADC for tuning the VFS. The tuning control unit controls the sub-ADC to convert plural reference voltages in the VFS tuning mode and extrapolating the conversion result to determine a corresponding calibrating VFS. The tuning control unit determines whether the calibrating VFS meeting the target VFS and loops the adjusting process in a linear search method or in a SAR method.

公开(公告)号：US12207009B2

公开(公告)日：2025-01-21

申请号：US18056755

申请日：2022-11-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shankar Ramakrishnan

IPC: H04N25/75 ,  H03M1/00 ,  H03M1/56 ,  H04N25/709

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

公开(公告)号：US12184303B2

公开(公告)日：2024-12-31

申请号：US17982352

申请日：2022-11-07

Applicant: HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED

Inventor： Jason Anthony Greenslade

IPC: H03M1/00 ,  H03M1/20 ,  H03M1/50 ,  H03M1/80

Abstract: A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

公开(公告)号：US20240396569A1

公开(公告)日：2024-11-28

申请号：US18672806

申请日：2024-05-23

Applicant: Cypress Semiconductor Corporation

Inventor： Eric SWINDLEHURST ,  Gajender Rohilla

IPC: H03M1/46 ,  H03M1/00 ,  H03M1/12

Abstract: A Successive Approximation Analog-to-Digital Converter (SAR_ADC) and method of operating the same are provided. Generally, the SAR_ADC includes a comparator having a first input to receive an input voltage (VIN), and a second input coupled to a n-bit capacitive digital-to-analog converter (DAC) to receive a voltage (VDAC), a Successive Approximation Register (SAR) coupled to a comparator output to provide n digital control signals to the DAC, and to store and output an n-bit binary-number approximating VIN, and a reference buffer to provide a voltage (VREF) to the DAC. The DAC sequentially drives each capacitance beginning with a most significant bit towards VREF, while the comparator compares the resulting VDAC to VIN, and the SAR sets or clears a current bit represented by the capacitance driven. The reference buffer includes adaptive power tuning to dynamically tune a drive-strength of the reference buffer based on the current bit.

公开(公告)号：US12143120B2

公开(公告)日：2024-11-12

申请号：US17976129

申请日：2022-10-28

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Jan Mulder ,  Frank Van Der Goes ,  Mohammadreza Mehrpoo ,  Sijia Wang

IPC: H03M1/66 ,  H03M1/74 ,  H03M1/00 ,  H03M1/08

Abstract: Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

公开(公告)号：US12047085B2

公开(公告)日：2024-07-23

申请号：US18077933

申请日：2022-12-08

Applicant: SiliconIntervention Inc.

Inventor： A. Martin Mallinson

IPC: H03M1/00 ,  G06F5/01 ,  G06F7/02 ,  H03F3/04 ,  H03F3/183 ,  H03F3/45 ,  H03G3/00 ,  H03K5/24 ,  H03M1/06 ,  H03M1/34 ,  H03M1/36

CPC classification number: H03M1/002 ,  G06F5/01 ,  G06F7/02 ,  H03F3/04 ,  H03F3/183 ,  H03F3/45089 ,  H03F3/45475 ,  H03G3/001 ,  H03K5/24 ,  H03M1/34 ,  H03M1/365 ,  H03F2203/45528 ,  H03M1/0682

Abstract: An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

公开(公告)号：US12040808B2

公开(公告)日：2024-07-16

申请号：US18077917

申请日：2022-12-08

Applicant: SiliconIntervention Inc.

Inventor： A. Martin Mallinson

IPC: H03F1/32 ,  G06F5/01 ,  G06F7/02 ,  H03F3/04 ,  H03G3/00 ,  H03K5/24 ,  H03M1/00 ,  H03M1/34

CPC classification number: H03M1/002 ,  G06F5/01 ,  G06F7/02 ,  H03F3/04 ,  H03G3/001 ,  H03K5/24 ,  H03M1/34

Abstract: An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

公开(公告)号：US20240178850A1

公开(公告)日：2024-05-30

申请号：US18284803

申请日：2022-03-29

Applicant: Viasat Inc.

Inventor： Gregory N. Kiesel

IPC: H03M1/00 ,  H04B17/345

CPC classification number: H03M1/007 ,  H04B17/345

Abstract: A first analog signal may be sampled during a first time period in accordance with a first sampling range and a sampling resolution step size, where a first digital sequence may be outputted during the first time period based on sampling the first analog signal.

公开(公告)号：US11973479B2

公开(公告)日：2024-04-30

申请号：US17508686

申请日：2021-10-22

Applicant: Radiawave Technologies Co., Ltd.

Inventor： Liuan Zhang ,  Yulin Tan ,  Jon Sweat Duster ,  Ning Zhang ,  Haigang Feng ,  Erkan Alpman

IPC: H03M1/00 ,  G11B20/10 ,  H03G3/00 ,  H03G3/30 ,  H03M1/18

CPC classification number: H03G3/3005 ,  G11B20/10027 ,  H03G3/001 ,  H03M1/185 ,  G11B20/10037

Abstract: Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.