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647 条记录 (耗时 0.018 秒)

    SELF-DIAGNOSIS CIRCUIT AND SEMICONDUCTOR DEVICE
    3.
    发明公开
    SELF-DIAGNOSIS CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240175922A1

    公开(公告)日：2024-05-30

    申请号：US18272432

    申请日：2022-01-12

    申请人： Rohm Co., Ltd.

    发明人： Ryosuke SUMII ,  Katsuhiro OSHIKAWA ,  Takayuki MATSUURA

    IPC分类号： G01R31/3187 ,  G01R31/28 ,  G01R31/319 ,  G01R31/3193

    CPC分类号： G01R31/3187 ,  G01R31/2856 ,  G01R31/2879 ,  G01R31/31901 ,  G01R31/31932

    摘要： A self-diagnosis circuit (BST1) configured to diagnose a fault detection circuit (20) including a first comparator (CMP1) configured to be fed with a voltage based on a fault sensing target voltage (Vo1) and a first reference voltage (Vref1) includes a voltage switch circuit (50) configured to switch the level of a voltage based on a second reference voltage (Vref2) and output the resulting voltage, a first path switch circuit (51) configured to switch between a path through which the voltage output from the voltage switch circuit is fed to the first comparator and a path through which the voltage based on the fault sensing target voltage is fed to the first comparator, and a control circuit (15) configured to control the voltage switch circuit and the path switch circuit.

    DETERMINATION DEVICE, TEST SYSTEM, AND GENERATION DEVICE
    4.
    发明公开
    DETERMINATION DEVICE, TEST SYSTEM, AND GENERATION DEVICE 审中-公开

    公开(公告)号：US20240133953A1

    公开(公告)日：2024-04-25

    申请号：US18459130

    申请日：2023-08-30

    申请人： Kioxia Corporation

    发明人： Mikio SHIRAISHI

    IPC分类号： G01R31/3193 ,  G01R31/317

    CPC分类号： G01R31/31932 ,  G01R31/31727 ,  G01R31/31935

    摘要： A determination device includes an estimation circuit and a determination circuit. The estimation circuit generates estimation data by estimating input data in the n-th cycle based on the input data in cycles prior to the n-th cycle and a first generator polynomial. The determination circuit determines whether the input data and the estimation data match. The first generator polynomial is an arithmetic expression that sets the estimation data in the n-th cycle to an inverted value of the input data in (n−1)-th cycle if a logical sum of all the input data in a first period corresponding to a preset number of cycles prior to the n-th cycle is 0 or a logical product of all the input data in a second period corresponding to the preset number of cycles prior to the n-th cycle is 1, and sets the estimation data in the n-th cycle to the same value as the input data in the (n−1)-th cycle if the logical sum is not 0 and the logical product is not 1.

    CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION
    5.
    发明公开
    CIRCUIT AND METHOD TO MEASURE SIMULATION TO SILICON TIMING CORRELATION 审中-公开

    公开(公告)号：US20240085475A1

    公开(公告)日：2024-03-14

    申请号：US18510835

    申请日：2023-11-16

    申请人： MediaTek Singapore Pte. Ltd.

    发明人： Ashish Kumar NAYAK ,  Hugh Thomas MAIR ,  Anshul VARMA ,  Anand RAJAGOPALAN

    IPC分类号： G01R31/317 ,  G01R31/30 ,  G01R31/3193 ,  H03K3/03 ,  H03K5/134

    CPC分类号： G01R31/31725 ,  G01R31/3016 ,  G01R31/31937 ,  H03K3/0315 ,  H03K5/134

    摘要： Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

    Circuit and method to measure simulation to silicon timing correlation
    6.
    发明授权
    Circuit and method to measure simulation to silicon timing correlation 有权

    公开(公告)号：US11835580B2

    公开(公告)日：2023-12-05

    申请号：US17397879

    申请日：2021-08-09

    申请人： MEDIATEK Singapore Pte. Ltd.

    发明人： Ashish Kumar Nayak ,  Hugh Thomas Mair ,  Anshul Varma ,  Anand Rajagopalan

    IPC分类号： H03K3/03 ,  G01R31/3193 ,  H03K5/134 ,  G01R31/317 ,  G01R31/30

    CPC分类号： G01R31/31725 ,  G01R31/3016 ,  G01R31/31937 ,  H03K3/0315 ,  H03K5/134

    摘要： Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

    Fault injection in a clock monitor unit
    8.
    发明授权
    Fault injection in a clock monitor unit 有权

    公开(公告)号：US11609833B2

    公开(公告)日：2023-03-21

    申请号：US17024798

    申请日：2020-09-18

    申请人： NXP USA, Inc.

    发明人： Praveen Durga ,  Parul Bansal

    IPC分类号： G06F11/27 ,  G01R31/317 ,  G06F11/263 ,  H03K5/22 ,  G06F1/04 ,  G01R23/15 ,  G01R31/3193 ,  G06F11/07 ,  G01R31/319 ,  G01R31/3187

    摘要： A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

    Multi-channel timing calibration device and method
    9.
    发明授权
    Multi-channel timing calibration device and method 有权

    公开(公告)号：US11531065B2

    公开(公告)日：2022-12-20

    申请号：US17460298

    申请日：2021-08-29

    申请人： YOUNGTEK ELECTRONICS CORPORATION

    发明人： Ching-Yung Tseng ,  Yu-Chih Cheng ,  Ping-Lung Wang

    IPC分类号： G01R31/319 ,  G01R31/3193

    摘要： A multi-channel timing calibration device and a method applicable thereto are provided. The device includes: a plurality of channel inputs, at least one relay switch, at least one comparator, at least one first multiplexer, and a time measurement chip. The at least one comparator is connected to the at least one relay switch, and connected to a reference voltage or a digital analog converter. The at least one first multiplexer has different signals for different channel groups and outputs a signal of a designated channel. The time measurement chip calculates a timing difference of each of the channels of each of the channel inputs as a basis for delay of the timing signals.

    SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-CHIPS
    10.
    发明申请
    SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-CHIPS 有权

    公开(公告)号：US20220334181A1

    公开(公告)日：2022-10-20

    申请号：US17301936

    申请日：2021-04-19

    申请人： NXP USA, Inc.

    发明人： Rohan Poudel ,  Anurag Jindal ,  Joseph Rollin Wright ,  Nipun Mahajan ,  Shruti Singla ,  Hemant Nautiyal

    IPC分类号： G01R31/317 ,  G01R31/3193 ,  G01R31/3185

    摘要： A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.