Hybrid method for high-speed serial link skew calibration

    公开(公告)号:US10936007B2

    公开(公告)日:2021-03-02

    申请号:US16374525

    申请日:2019-04-03

    摘要: A method for reducing a clock-data skew in a serial interface. A clock signal and a data signal are received through the serial interface at first and second inputs of an exclusive OR (XOR) averaging (XOR-averaging) gate. An output of the XOR-averaging gate is determined and compared with a target value. At least one of a delay of the clock signal and a delay of the data signal is determined based on comparing the output of the XOR-averaging gate with the target value. A skew between the clock signal and the data signal is reduced by delaying at least one of the clock signal and the data signal.

    PIXEL ARRAY WITH ISOLATED PIXELS
    92.
    发明申请

    公开(公告)号:US20210057466A1

    公开(公告)日:2021-02-25

    申请号:US16548697

    申请日:2019-08-22

    发明人: Qin Wang Gang Chen

    IPC分类号: H01L27/146

    摘要: A pixel array includes a semiconductor substrate, a plurality of isolation layer segments, and a plurality of photodiodes. Each of the plurality of isolation layer segments extends through the semiconductor substrate in a first direction. Each of the plurality of isolation layer segments encloses a portion of the semiconductor substrate in a plane perpendicular to the first direction. The plurality of isolation layer segments form a grid that defines a plurality of isolated sections of the semiconductor substrate. The plurality of isolated sections of the semiconductor substrate include the portions of the semiconductor substrate. Each of the photodiodes is formed in a respective one of the plurality of isolated sections of the semiconductor substrate.

    Low complexity loudness equalization

    公开(公告)号:US10924077B2

    公开(公告)日:2021-02-16

    申请号:US16116305

    申请日:2018-08-29

    摘要: An electronic device to equalize sound includes a microphone coupled to receive the sound and output sound data. The sound has amplitude that changes with respect to time, and the sound includes one or more frequencies. The sound data indexes the amplitude with respect to the time. The electronic device also includes a controller coupled to microphone, and the controller includes logic that when executed by the controller causes the electronic device to perform operations. The operations may include: receiving the sound data from the microphone with the controller; adjusting the amplitude of the sound included in the sound data across the one or more frequencies using a filter disposed in the logic; and outputting filtered sound data.

    Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors

    公开(公告)号:US10834352B2

    公开(公告)日:2020-11-10

    申请号:US16247475

    申请日:2019-01-14

    摘要: An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.

    Bias circuit for use with divided bit lines

    公开(公告)号:US10819936B2

    公开(公告)日:2020-10-27

    申请号:US16275092

    申请日:2019-02-13

    摘要: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.

    Image sensor testing probe card
    98.
    发明授权

    公开(公告)号:US10775413B2

    公开(公告)日:2020-09-15

    申请号:US15285731

    申请日:2016-10-05

    IPC分类号: G01R31/311 G01R1/073 G01R3/00

    摘要: A method of increasing uniformity in light from a light source at a plurality of targets of the light includes locating a plurality of movable aperture elements between the light source and the targets. Each aperture element defines an aperture through which the light passes from the light source to an associated one of the plurality of targets associated with the aperture element along a longitudinal axis of the aperture element. The method also includes moving at least one of the aperture elements along its longitudinal axis to change a feature of light incident on the target associated with the aperture element.

    Interposer and chip-scale packaging for wafer-level camera

    公开(公告)号:US10734437B2

    公开(公告)日:2020-08-04

    申请号:US16267370

    申请日:2019-02-04

    IPC分类号: H01L27/146

    摘要: A chip-scale packaging process for wafer-level camera manufacture includes aligning an optics component wafer with an interposer wafer having a photoresist pattern that forms a plurality of transparent regions, bonding the aligned optics component wafer to the interposer wafer, and dicing the bonded optics component wafer and interposer wafer such that each optics component with interposer has a transparent region. The process further includes dicing an image sensor wafer, aligning the pixel array of each image sensor with the transparent region of a respective optics component with interposer, and bonding each image sensor to its respective optics component with interposer. Each interposer provides alignment between its respective optics component center and its respective pixel array center of the image sensor based on the respective transparent region. The interposer further provides a back focal length for focusing light from the optics component onto a top surface of the pixel array.

    CODE PATTERN FOR REPRESENTING TRACING NUMBER OF CHIP

    公开(公告)号:US20200243472A1

    公开(公告)日:2020-07-30

    申请号:US16257136

    申请日:2019-01-25

    摘要: A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern of a first group and at least one code pattern of a second group formed on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the code patterns are visible from a backside of the chip, and wherein a tracing number of the chip is represented by the code patterns.