Abstract:
Tunneling-enhanced, floating gate semiconductor devices and methods for forming such devices are described. In one embodiment, a p-n junction device is formed with a floating gate that is partially doped with n- and p-type impurities. Two regions on either side of an n+ doped region in the floating gate and a surface region on a substrate are implanted with the impurities based on a number of predetermined configurations. In another embodiment, a transistor type semiconductor device is configured with implanted impurities in two regions of its floating gate as well as two surface regions in its substrate. Enhanced tunneling junction enables use of lower tunneling voltages in applications such as programming NVM cells.
Abstract:
The invention provides a cyclic single-chain trispecific antibody against human tumor. It comprises three parts. The first part is an anti-tumor Fab antibody, an anti-tumor single-domain antibody or an scFv. The second part is a reshaped Fab antibody against human CD3, a reshaped single-domain antibody against human CD3 or a reshaped scFv against human CD3. The third part is a reshaped Fab antibody against human CD28, a reshaped single-domain antibody against human CD28 or a reshaped scFv against human CD28. The present invention also offers the DNA sequence coding for this trispecific antibody, expression vectors containing this DNA sequence and host cells (E. coli) containing the vectors.
Abstract:
The present invention provides compounds, including resolved enantiomers, diastereomers, solvates and pharmaceutically acceptable salts thereof, comprising the Formula: A-L-CR where CR is a cyclical core group, L is a linking group and A is as defined herein. Also provided are methods of using the compounds of this invention as AKT protein kinase inhibitors and for the treatment of hyperproliferative diseases such as cancer.
Abstract:
With analysis data in the prior art, it is difficult to find out if a change regarded as a judgmental standard of the completion of seasoning has come from a change due to the seasoning, namely, change in condition of the interior of a processing container or come from another change based on a temperature change among respective dummy wafers and furthermore, it is difficult to judge whether the seasoning has been completed or not. Therefore, a plasma processing method of the present invention, which is a method for detecting the completion of seasoning in performing the seasoning by loading dummy wafers W into a processing container 2 of a plasma processing apparatus 1, includes a process of creating a predictive formula for predicting the completion of seasoning and another process of detecting the completion of seasoning in performing the seasoning, based on the predictive formula. The creation of the predictive formula is accomplished by performing a multivariate analysis against a plurality of measured data that can be obtained by first supplying dummy wafers W into the processing container 2, cooling down the interior of the processing container 2 and supplying a plurality of dummy wafers W into the processing container 2 again.
Abstract:
An auto feedback and photo attenuation structure of a vertical cavity surface emitting laser (VCSEL) includes a VCSEL combined with a monitor photodetector (MPD). The thickness of the absorbing layer of the MPD may be adjusted, so that when output light of different wavelengths passes through the MPD, a portion of light may be absorbed by the absorbing layer to function as a feedback path of an auto power control, and a portion of light may penetrate through the absorbing layer, and may satisfy the requirement of the eye safety class I. The thickness of the absorbing layer of the MPD may be controlled precisely, thereby increasing the quality of products and decreasing cost of fabrication.
Abstract:
In this invention two compression circuits are combined to produce at a single output pass/fail condition for a plurality of memory addresses and a plurality of I/O. The output of an address compression circuit is connected to an I/O circuit. An I/O compression circuit is connected to several I/O circuits and the output of the I/O compression circuit controls a selected data output driver to provide a combined test result of the plurality of addresses and the plurality of I/O. The combination of the two compression circuits is made possible because the address data compression circuits and the I/O compression circuits use different truth tables.
Abstract:
A pay phone box structure includes a casing having a first side wall and a second side wall, a first supporting plate fixedly mounted on the first side wall of the casing and containing a plurality of first locking slots, a second supporting plate fixedly mounted on the second side wall of the casing and containing a plurality of second locking slots, a suspension bar secured to the second supporting plate and having a plurality of first locking hooks each detachably received in thesecond locking slots, a pivot plate pivotally mounted on the suspension bar and having an upper end portion and a lower end portion, a cover pivotally mounted on the casing and having a first side wall, a second side wall secured to the pivot plate, a closed wall and an open wall, a sliding plate slidably mounted on the first side wall of the cover and having a plurality of second locking hooks each detachably received in thefirst locking slots, and a U-shaped pivot bar pivotally mounted on the closed wall of the cover and having a first leg pivotally connected with the sliding plate and a second leg pivotally connected with the lower end portion of the pivot plate.
Abstract:
A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock. The delay control means will create a first phase control pulse and a second phase control pulse. A duty cycle synchronizer means is connected to the delay control means to create the dual phases of the internal clock from the first phase control pulse and the second phase control pulse. An internal buffer will buffer and amplify the two phases of the internal clock signal that is aligned with the external clock signal to have minimum skew.
Abstract:
Methods of inducing genetic material into cells of an individual and compositions and kits for practicing the same are disclosed. The methods comprise the steps of contacting cells of an individual with a polynucleotide function enhancer and administering to the cells, a nucleic acid molecule that is free of retroviral particles. The nucleic acid molecule comprises a nucleotide sequence that encodes a protein that comprises at least one epitope that is identical or substantially similar to an epitope of a pathogen antigen or an antigen associated with a hyperproliferative or autoimmune disease, a protein otherwise missing from the individual due to a missing, non-functional or partially functioning gene, or a protein that produces a therapeutic effect on an individual. Methods of prophylactically and therapeutically immunizing an individual against HIV are disclosed. Pharmaceutical compositions and kits for practicing methods of the present invention are disclosed.
Abstract:
Bicycle chain plate includes an inner plate having a pair of protruding portions at respective ends of on one side thereof adopted to be inserted into two holes of an outer plate, respectively. The outer plate has also a pair of prtoruding portions at respective ends of one side thereof adopted also to be inserted into two holes of the inner plate so that the inner and outer plates are securely fastened.