公开(公告)号：US08039952B2

公开(公告)日：2011-10-18

申请号：US12472340

申请日：2009-05-26

Applicant: Donald R. Mullen ,  Ming Li

Inventor： Donald R. Mullen ,  Ming Li

IPC: H05K7/20

CPC classification number: H05K1/0206 ,  H01L23/3677 ,  H01L2224/32225 ,  H05K1/141 ,  H05K2201/066 ,  H05K2201/10371 ,  H05K2203/1572

Abstract: The system includes a circuit board, a semiconductor module, a heat dissipator, and at least one thermal via. The circuit board has substantially flat opposing first and second sides. The semiconductor module includes multiple semiconductor devices. The semiconductor module is oriented substantially parallel to the circuit board near the first side, while the heat dissipator is disposed near the second side. The thermal via extends through the circuit board to thermally couple the semiconductor module to the heat dissipator, which may be a heat spreader, heat sink, cooling fan, or heat pipe.

Abstract translation: 该系统包括电路板，半导体模块，散热器和至少一个热通孔。 电路板具有基本平坦的相对的第一和第二侧面。 半导体模块包括多个半导体器件。 半导体模块在第一侧附近基本上平行于电路板取向，而散热器设置在第二侧附近。 热通孔延伸穿过电路板，以将半导体模块热耦合到散热器，散热器可以是散热器，散热器，冷却风扇或热管。

公开(公告)号：US20110248376A1

公开(公告)日：2011-10-13

申请号：US13166867

申请日：2011-06-23

Applicant: Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

Inventor： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

IPC: H01L29/06

CPC classification number: H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Abstract translation: 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US08014067B2

公开(公告)日：2011-09-06

申请号：US12364252

申请日：2009-02-02

Applicant: Ming Li ,  Song Peng

Inventor： Ming Li ,  Song Peng

IPC: G02B5/30 ,  G02B27/28

CPC classification number: H04Q11/0005 ,  G02B6/272 ,  H04Q2011/0024 ,  H04Q2011/0026 ,  H04Q2011/0035

Abstract: An improved optical switch utilizes one polarization modulator, with the beam components traversing it twice. Because of the twice traverse, the extinction ratio of the switch is doubled without the addition of another polarization modulator, thus avoiding the costs of additional optical components. With no additional components, the switch is more compact than conventional switches with the same extinction ratio. Fewer components also result in more thermal and long-term stability and less crosstalk.

Abstract translation: 改进的光开关利用一个偏振调制器，光束分量穿过它两次。 由于两次横移，所以开关的消光比加倍而不增加另一个偏振调制器，从而避免了额外的光学元件的成本。 没有附加组件，开关比具有相同消光比的常规开关更紧凑。 更少的组件也导致更多的热和长期稳定性和更少的串扰。

公开(公告)号：US08008141B2

公开(公告)日：2011-08-30

申请号：US12503594

申请日：2009-07-15

Applicant: Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

Inventor： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC: H01L21/8232

CPC classification number: H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

Abstract: A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

Abstract translation: 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US20110191167A1

公开(公告)日：2011-08-04

申请号：US12700530

申请日：2010-02-04

Applicant: Deepak K. Agarwal ,  Dz-Mou Jung ,  Sai-Ming Li ,  Mohammad Mahdian ,  R. Preston McAfee ,  Shanmugasundaram Ravikumar ,  David Reiley

Inventor： Deepak K. Agarwal ,  Dz-Mou Jung ,  Sai-Ming Li ,  Mohammad Mahdian ,  R. Preston McAfee ,  Shanmugasundaram Ravikumar ,  David Reiley

IPC: G06Q30/00 ,  G06Q10/00

CPC classification number: G06Q30/0246 ,  G06Q30/0275

Abstract: According to some example embodiments, a method includes calculating learning values associated with a plurality of listings, at least one of said learning values associated with one of said listings representing a value based, at least in part, on a probability distribution of selections of said listing. The method further includes applying said learning values to ranking scores associated with said listings to provide an updated ranking, and electronically auctioning advertising inventory to purchasers associated with said listings based, at least in part, on said updated ranking.

Abstract translation: 根据一些示例性实施例，一种方法包括计算与多个列表相关联的学习值，所述学习值中的至少一个与所述列表中的一个相关联，表示至少部分地基于所述列表的选择的概率分布 清单。 该方法还包括将所述学习值应用于与所述列表相关联的排名分数以提供更新的排名，以及至少部分地基于所述更新的排名，向与所述列表相关联的购买者电子拍卖广告库存。

公开(公告)号：US07987588B2

公开(公告)日：2011-08-02

申请号：US12273550

申请日：2008-11-19

Applicant: Kuan-Jui Huang ,  Chang-Ping Wang ,  Hsiu-Ming Li ,  Shih-Min Huang ,  Hui-Chen Kuo ,  Chia-Chun Chen

Inventor： Kuan-Jui Huang ,  Chang-Ping Wang ,  Hsiu-Ming Li ,  Shih-Min Huang ,  Hui-Chen Kuo ,  Chia-Chun Chen

IPC: H05K3/02

CPC classification number: H01L25/0657 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/15 ,  H01L2224/14 ,  H01L2224/16237 ,  H01L2224/48137 ,  H01L2224/4823 ,  H01L2224/49109 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

Abstract translation: 本发明公开了一种用于连接多个芯片的插入器。 插入器包括连接基板和设置在连接基板中的至少通孔。 连接基板具有第一表面和第二表面。 通孔作为连接器，并且电连接到第一表面和第二表面。 第一表面和第二表面分别电连接至至少第一芯片和第二芯片。 此外，第一芯片和第二芯片通过通孔电连接。

公开(公告)号：US20110168554A1

公开(公告)日：2011-07-14

申请号：US13070767

申请日：2011-03-24

Applicant: QI HAU ZHANG ,  Ming Li ,  Chorng Shry Niou ,  Scott Liao

Inventor： QI HAU ZHANG ,  Ming Li ,  Chorng Shry Niou ,  Scott Liao

IPC: C23C14/34

CPC classification number: G01N23/2276 ,  H01L22/12

Abstract: An apparatus for treatment of a sample for the manufacture of integrated circuits includes a holder apparatus and a stage which is coupled to the holder apparatus. The stage is capable of holding a portion of a sample to be analyzed. The apparatus also includes a shield that is operably coupled to the stage to block a portion of the sample. The shield is capable of movement relative to the sample to block one or more portions of the sample. The shield is provided on a track member and is movable from a first spatial location to a second spatial location on the track member. The apparatus further includes an enclosure surrounding an entirety of the sample and the shield.

Abstract translation: 用于处理用于制造集成电路的样品的装置包括保持装置和与保持装置连接的台。 该阶段能够容纳要分析的样品的一部分。 该装置还包括可操作地耦合到载物台以阻挡样品的一部分的屏蔽件。 屏蔽能够相对于样品移动以阻挡样品的一个或多个部分。 屏蔽件设置在轨道构件上并且可从轨道构件上的第一空间位置移动到第二空间位置。 该装置还包括围绕整个样品和屏蔽件的外壳。

公开(公告)号：US20110133418A1

公开(公告)日：2011-06-09

申请号：US12951162

申请日：2010-11-22

Applicant: Fang Ming LI

Inventor： Fang Ming LI

IPC: B62B9/20 ,  F16C11/04

CPC classification number: B62B7/06 ,  B62B9/104 ,  B62B9/24 ,  B62B2205/00 ,  Y10T403/1608 ,  Y10T403/1616

Abstract: A joint structure having an anti-pinch safety feature comprises a first support element and a second support element, and a joint structure including a coupling socket and an anti-pinch element. The coupling socket is respectively connected with the first and second support element. The anti-pinch element is interposed between the second support element and the coupling socket. The second support element when rotating about a pivot axis relative to the coupling socket forms a pinch region between an edge of the coupling socket and the second support element, and the anti-pinch element can continuously occlude the pinch region when the second support element is rotating. The joint structure can be suitable for use in a support frame of an infant carrier apparatus.

Abstract translation: 具有防夹紧安全特征的接合结构包括第一支撑元件和第二支撑元件，以及包括联接插座和反夹紧元件的接合结构。 联接插座分别与第一和第二支撑元件连接。 抗夹紧元件插入在第二支撑元件和联接插座之间。 第二支撑元件当围绕枢转轴线相对于联接插座旋转时形成在联接插座的边缘和第二支撑元件之间的夹紧区域，并且当第二支撑元件是第二支撑元件是第二支撑元件时，反夹紧元件可以连续地闭合夹紧区域 旋转。 接头结构可适用于婴儿背带装置的支撑框架。

公开(公告)号：US07935566B2

公开(公告)日：2011-05-03

申请号：US12600151

申请日：2008-05-14

Applicant: Chang Ming Li ,  Mary Bee Eng Chan ,  Jun Zhang

Inventor： Chang Ming Li ,  Mary Bee Eng Chan ,  Jun Zhang

IPC: H01L51/40 ,  H01L21/00

CPC classification number: H01L51/0004 ,  H01L51/0021 ,  H01L51/102

Abstract: A method of fabricating an organic field effect transistor (OFET) includes forming at least one OFET structure by ultraviolet (UV) transfer embossing printing, where, in an example embodiment, the method includes providing ink material on at least part of a patterned surface of a mold, where the mold 100 is then contacted on a coating of ultraviolet (UV) curable resin on a substrate so as to insert at least part of the ink material into the resin, the resin is then irradiated with UV light, and the mold is separated from the resin so as to transfer the ink material onto the substrate to form at least one OFET structure.

Abstract translation: 制造有机场效应晶体管（OFET）的方法包括通过紫外（UV）转印压花印刷形成至少一种OFET结构，其中在一个示例性实施方案中，该方法包括在至少部分图案化表面上提供油墨材料 模具，其中模具100然后在基材上的紫外线（UV）可固化树脂涂层上接触，以将至少部分油墨材料插入树脂中，然后用UV光照射树脂，模具 与树脂分离，以便将油墨材料转移到基材上以形成至少一种OFET结构。

公开(公告)号：US20110097386A1

公开(公告)日：2011-04-28

申请号：US12715203

申请日：2010-03-01

Applicant: Solomon S. Steiner ,  Robert Hauser ,  Ming Li ,  Robert Feldstein ,  Roderike Pohl

Inventor： Solomon S. Steiner ,  Robert Hauser ,  Ming Li ,  Robert Feldstein ,  Roderike Pohl

IPC: A61K38/26 ,  A61K9/127 ,  A61P3/08

CPC classification number: A61K38/26 ,  A61K9/0019 ,  A61K9/1075 ,  A61K9/127 ,  A61K9/19 ,  A61K47/24

Abstract: A formulation composed of a sugar such as glucose and a surfactant such as myristoyl lysophosphocholine (LMPC) has been designed to stabilize both hydrophilic and hydrophobic portions of the glucagon molecule, under prolonged physiological conditions, in a formulation that is sufficiently similar to the pH and osmolarity of plasma so as not to induce or to minimize site irritation. The combination of a simple sugar and an surfactant stabilizes the glucagon molecule in an aqueous solution for seven days at 37° C.

Abstract translation: 已经设计了由糖如葡萄糖和表面活性剂如肉豆蔻酰溶血磷脂酰胆碱（LMPC）组成的制剂，以在长时间的生理条件下稳定胰高血糖素分子的亲水部分和疏水部分，其浓度与pH和pH足够相似， 血浆的渗透压，以免诱发或最小化部位刺激。 单糖和表面活性剂的组合使得胰高血糖素分子在37℃下在水溶液中稳定7天。