公开(公告)号：US20240332413A1

公开(公告)日：2024-10-03

申请号：US18612646

申请日：2024-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Ferdinando IUCOLANO ,  Alessandro CHINI ,  Maria Eloisa CASTAGNA ,  Aurore CONSTANT ,  Cristina TRINGALI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462

Abstract: The HEMT device has a body including a heterostructure configured to generate a 2-dimensional charge-carrier gas; and a gate structure which extends on a top surface of the body and is biasable to electrically control the 2-dimensional charge-carrier gas. The gate structure has a channel modulating region of semiconductor material; a functional region of semiconductor material; and a gate contact region of conductive material. The functional region and the gate contact region extend on a top surface of the channel modulating region and the gate contact region is arranged laterally with respect to the functional region. The channel modulating region has a different conductivity type with respect to the functional region.

公开(公告)号：US20240332250A1

公开(公告)日：2024-10-03

申请号：US18615039

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Antonio BELLIZZI ,  Guendalina CATALANO

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/98 ,  H01L2224/2746 ,  H01L2224/29111 ,  H01L2224/97 ,  H01L2224/98 ,  H01L2924/301

Abstract: Semiconductor chips are arranged on a first surface of a common electrically conductive substrate having an opposite second surface. The substrate includes adjacent substrate portions having mutually facing sides with sacrificial connecting bars extending between adjacent mutually facing sides. A solderable metallic layer is present on the second surface extending over the sacrificial connecting bars. The solderable metallic layer is selectively removed (by laser ablation or etching, for example) from at least part of the length the sacrificial connecting bars. The common electrically conductive substrate is then cut along the length of the elongate sacrificial connecting bars to provide singulated individual semiconductor devices. Undesired formation of electrically conductive filaments or flakes bridging parts of the substrate intended to be mutually isolated is countered.

公开(公告)号：US20240332162A1

公开(公告)日：2024-10-03

申请号：US18616696

申请日：2024-03-26

Applicant: STMicroelectronics International N.V.

Inventor： William THIES ,  Gilles GASIOT ,  Andrea PAGANINI ,  Jerome DEROO ,  Matteo REPOSSI

IPC: H01L23/522 ,  H03H7/01

CPC classification number: H01L23/5223 ,  H01L23/5225 ,  H03H7/0115

Abstract: A device includes a substrate and an interconnection network on the substrate. The interconnection network includes at least a first level, at least a second level and a third level. The first level includes one or more capacitors. The third level includes a metallic shield. The second level is positioned between the first level and the substrate. The capacitors of the first level are entirely separated from the substrate by the shield. The second level is located between the first and third levels.

公开(公告)号：US20240332143A1

公开(公告)日：2024-10-03

申请号：US18429009

申请日：2024-01-31

Applicant: STMicroelectronics International N.V.

Inventor： Jing-En LUAN

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/49558 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49513 ,  H01L23/49517 ,  H01L24/83 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2224/83

Abstract: A hybrid QFN package includes an encapsulant body that encapsulates a lead frame and integrated circuit (IC) device where the lead frame includes a die pad and vertically offset leads. Back sides of the die pad and encapsulant body are coplanar at first surface. Front sides of the leads, the IC device and the encapsulant body are substantially coplanar at a second surface. An insulating layer covers the second surface except at a portion of the leads located at the peripheral edge of the encapsulating body. Vias extend through the insulating layer to the leads and IC device. Wiring lines on the insulating layer interconnect the vias. A passivation layer covers the wiring lines and vias.

公开(公告)号：US20240332106A1

公开(公告)日：2024-10-03

申请号：US18614989

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Paolo CREMA ,  Alberto ARRIGONI

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/3142 ,  H01L21/56 ,  H01L23/49503

Abstract: A semiconductor die is arranged at a first surface of a die pad. The die pad has a peripheral edge and a second surface opposite to the first surface that includes a first region and a second region surrounding the first region. The second region extends to the peripheral edge of the die pad from a border line at the first region and includes a recessed formation extending continuously along the border line. An insulating encapsulation is molded onto the die pad with the first region of the second surface left uncovered and the second region of the second surface of the die pad being covered by the insulating encapsulation that fills the recessed formation. The recessed formation has a variable recess depth between the border line and the peripheral edge of the die pad to provide an extended length delamination path from the border line to the semiconductor die.

公开(公告)号：US20240331767A1

公开(公告)日：2024-10-03

申请号：US18614460

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Anuj DHILLON

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: The present disclosure is directed to a device and method for accurately estimating a write self-time of a memory array. The write self-time is estimated by performing a simulated write operation on a write self-time bit cell having the same structure and arrangement as each of the bit cells of the memory array. The write operations on the bit cells of the memory array are stopped in response to detecting completion of the simulated write operation.

公开(公告)号：US20240330153A1

公开(公告)日：2024-10-03

申请号：US18602977

申请日：2024-03-12

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alessandro BASTONI

IPC: G06F11/36

CPC classification number: G06F11/3636

Abstract: Method for monitoring the execution of an application software implementing a safety function, comprising implementing a software-based lock step on a dual asymmetrical processing units structure, the processing units structure including a first processing unit and a second processing unit having, due to the asymmetry, a different hardware structure and/or lower computations capability with respect to the first processing unit. A first runtime software is executed on the first processor while a second runtime software being a potentially modified version of the first runtime software and having the same behavior as that of the first runtime software, is executed on the second processor.

公开(公告)号：US20240329098A1

公开(公告)日：2024-10-03

申请号：US18615233

申请日：2024-03-25

Applicant: STMicroelectronics International N.V.

Inventor： Roberto TIZIANI ,  Francesca DE VITI

IPC: G01R15/20 ,  G01R19/00 ,  H01L21/8234 ,  H01L23/31

CPC classification number: G01R15/207 ,  G01R15/202 ,  G01R19/0092 ,  H01L21/8234 ,  H01L23/3121

Abstract: An insulating encapsulation encapsulates a semiconductor die having an integrated Hall current sensor configured to measure an electric current flowing adjacent an active surface of the semiconductor die. An electrically conductive trace is embedded in the insulating encapsulation. First electrically conductive formations extend through the insulating encapsulation towards opposed ends of the electrically conductive trace. The first electrically conductive formations are configured to cause an electrical current subject to measurement to flow in a current flow path through the electrically conductive trace. Second electrically conductive formations extend through the insulating encapsulation towards the active surface of the semiconductor die. The second electrically conductive formations are configured to activate the Hall current sensor integrated in the semiconductor die.

公开(公告)号：US12107486B2

公开(公告)日：2024-10-01

申请号：US18234137

申请日：2023-08-15

Applicant: STMicroelectronics International N.V.

Inventor： Akshat Jain

IPC: H02M1/08 ,  H02M1/32 ,  H03K17/082 ,  H05B6/10 ,  H02M7/04

CPC classification number: H02M1/08 ,  H02M1/32 ,  H03K17/0828 ,  H05B6/108 ,  H02M7/04

Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

公开(公告)号：US20240321795A1

公开(公告)日：2024-09-26

申请号：US18603113

申请日：2024-03-12

Applicant: STMicroelectronics International N.V.

Inventor： Olivier ORY ,  Michael DE CRUZ

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/463 ,  H01L21/768 ,  H05K1/18

CPC classification number: H01L24/13 ,  H01L21/288 ,  H01L21/463 ,  H01L21/76865 ,  H01L24/29 ,  H01L24/73 ,  H05K1/181 ,  H01L2224/13007 ,  H01L2224/13025 ,  H01L2224/29005 ,  H01L2224/2919 ,  H01L2224/73153 ,  H01L2924/01029

Abstract: The present disclosure relates to a method of manufacturing first electronic components, each comprising a second electronic component, each second component comprising at least two contact metallizations, the method comprising: a) forming, on a substrate, at least two metal pillars; b) forming, over a portion of the surface of each pillar, a metallization of the component; c) covering the surface of the substrate, the pillars, and the metallizations of the first components with a first resin layer; d) removing the substrate to expose a surface of the pillars, opposite to the metallizations of the components; e) bonding and electrically connecting the second components, by their metallizations, to the surface of the pillars opposite to the metallizations of the first components; and f) expose the surface of the metallizations of the first components opposite to the pillars.